Dynamic State-Retention Flip-Flop for Fine-Grained Power Gating With Small Design and Power Overhead

Henzler, Stephan; Georgakos, Georg; Eireiner, Matthias; Nirschl, T.; Pacha, C.; Berthold, J.; Schmitt‐Landsiedel, D.

doi:10.1109/jssc.2006.873218

Cited by 20 publications

(4 citation statements)

References 6 publications

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“…During the active cycles, though the static power is consumed in the cells, it can be minimized by reducing the number of cells that are powered by PL, i.e., by a fine-grained power gating. 20,21) Here, we compare the proposed 4T-2MTJ cell with the 8T-2MTJ cell 17) that operates as a 6T-SRAM cell in read/ write and the data is saved into the STT-MTJ prior to powerdown. The 8T-2MTJ cell has a benefit of higher programming speed with smaller operation power than the proposed 4T-2MJ cell that saves and loads data each time it is accessed.…”

Section: Cell Structure and Its Operationmentioning

confidence: 99%

High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction

Ohsawa

Iga

Ikeda

et al. 2012

Jpn. J. Appl. Phys.

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A novel nonvolatile static random access memory cell is proposed that consists of four transistors and two spin-transfer-torque magnetic tunnel junctions (STT-MTJs). In the case of the NFET driver cell, the free layers of the magnetic tunnel junctions are connected to the transistors' sources and drains to make the cell read-disturb free. The static power is totally eliminated as the power line is shut down during data hold. The static noise margin of the cell is calculated based on the experimental data on MTJ switching that is enhanced from the resistive load SRAM cell due to the MTJ's switching operation. The cell size is estimated to become smaller than the 6-transistor SRAM cell when it is designed at 45 nm node and beyond owing to the MTJ's area shrink as well as the thinning of its tunnel dielectrics (MgO).

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Section: Cell Structure and Its Operationmentioning

confidence: 99%

High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction

Ohsawa

Iga

Ikeda

et al. 2012

Jpn. J. Appl. Phys.

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“…This poses serious problems when storing values in memory elements and when interfacing powergated to non power-gated regions. Solutions based on the usage of special types of memory elements [3] or by proper design of the sleep transistor cell [16] do exist.…”

Section: Power-gating and Aging Reductionmentioning

confidence: 99%

Power-Gating for Leakage Control and Beyond

Calimera¹,

Macii²,

Macii³

et al. 2014

Circuit Design for Reliability

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The need of reliable nanometric integrated circuits is driving the EDA community to develop new automated design techniques in which power consumption and variability are central objectives of the optimization flow.Although several Design-for-Low-Power and Design-for-Variability options are already available in modern EDA suites, the contrasting nature of the two metrics makes their integration extremely challenging. Most of the approaches used to compensate and/or mitigate circuit variability (e.g., Dynamic Voltage Scaling and Adaptive Body Biasing) are, in fact, intrinsically power inefficient, as they exploit the concept of redundancy, which is known to originate power overhead.In this work, we introduce possible solutions for concurrent leakage minimization and variability compensation. More specifically, we propose Power-Gating as a mean for simultaneously controlling static power consumption and mitigating the effects induced by two of the most insidious sources of variability, namely, Process Variations (PV) due to uncertainties in the manufacturing and Transistor Aging due to Negative Bias Temperature Instability (NBTI).We show that power-gating, when implemented through the insertion of dedicated switches (called sleep transistors), has a double effect: On one hand, when sleep transistors are enhanced with tunable features, it acts as a natural supplyvoltage regulator, which implements a control knob for PV compensation; on the other hand, during the idle periods, it makes the circuits immune to NBTI-induced aging.We describe optimization techniques for the integration of a new concept of power-gating into modern sub-45 nm design flows, that is, Variation-Aware PowerGating. The experimental results we have obtained are extremely promising, since they show 100 % timing yield under the presence of PV and circuit lifetime extension of more than 5 in the presence of NBTI.

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“…Several types of circuit can retain data without explicit control. This is achieved to some extent by the dynamic retention flip-flop [Henzler et al 2006], which eliminates the need for a sleep control signal by preserving its state in internal DRAM cells, but the period of retention is very short.…”

Section: Storage Retentionmentioning

confidence: 99%

Power gating

Shin

Seomun

Choi

et al. 2010

ACM Trans. Des. Autom. Electron. Syst.

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Power gating has become one of the most widely used circuit design techniques for reducing leakage current. Its concept is very simple, but its application to standard-cell VLSI designs involves many careful considerations. The great complexity of designing a power-gated circuit originates from the side effects of inserting current switches, which have to be resolved by a combination of extra circuitry and customized tools and methodologies. In this tutorial we survey these design considerations and look at the best practice within industry and academia. Topics include output isolation and data retention, current switch design and sizing, and physical design issues such as power networks, increases in area and wirelength, and power grid analysis. Designers can benefit from this tutorial by obtaining a better understanding of implications of power gating during an early stage of VLSI designs. We also review the ways in which power gating has been improved. These include reducing the sizes of switches, cutting transition delays, applying power gating to smaller blocks of circuitry, and reducing the energy dissipated in mode transitions. Power gating has also been combined with other circuit techniques, and these hybrids are also reviewed. Important open problems are identified as a stimulus to research.

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Dynamic State-Retention Flip-Flop for Fine-Grained Power Gating With Small Design and Power Overhead

Cited by 20 publications

References 6 publications

High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction

High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction

Power-Gating for Leakage Control and Beyond

Power gating

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