Early stopping criterion for message-passing decoding of LDLC

Xu, Jin; Duan, Can; Zhao, Dixian; Wang, Yan; Xie, Feng

doi:10.1109/icact.2015.7224811

Cited by 2 publications

(4 citation statements)

References 9 publications

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“…The decoded integer vector, b , is computed after every decoding iteration and the iterative decoding process is terminated as soon as decoding is successful. Early stopping reduces the average number of iterations required for decoding and is commonly used in iterative decoding [17,[22][23][24][25].…”

Section: Final Decisionmentioning

confidence: 99%

“…The emphasis of the literature to date in [1,[9][10][11][12][13][14][15][16][17] is on demonstrating theoretically achievable performance limits of LDLCs; not much work has been done towards a hardware implementation of LDLC decoding. Our work contributes in this direction with the aim to achieve a hardware implementation of a decoder for LDLCs.…”

Section: Introductionmentioning

confidence: 99%

“…Figure 17. Timing diagram of block used in variable node message processing block of architecture C. The waveforms are shown particularly for block.…”

mentioning

confidence: 99%

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Hardware Implementation of a Fixed-Point Decoder for Low-Density Lattice Codes

Srivastava

Gaudet

Mitran

2022

J Sign Process Syst

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This paper describes a field-programmable gate array (FPGA) implementation of a fixed-point low-density lattice code (LDLC) decoder where the Gaussian mixture messages that are exchanged during the iterative decoding process are approximated to a single Gaussian. A detailed quantization study is first performed to find the minimum number of bits required for the fixed-point decoder to attain a frame error rate (FER) performance similar to floating-point. Then efficient numerical methods are devised to approximate the required non-linear functions. Finally, the paper presents a comparison of the performance of the different decoder architectures as well as a detailed analysis of the resource requirements and throughput trade-offs of the primary design blocks for the different architectures. A novel pipelined LDLC decoder architecture is proposed where resource re-utilization along with pipelining allows for a parallelism equivalent to 50 variable nodes on the target FPGA device. The pipelined architecture attains a throughput of 10.5 Msymbols/sec at a distance of 5 dB from capacity which is a 1.8$$\times$$ × improvement in throughput compared to an implementation with 20 parallel variable nodes without pipelining. This implementation also achieves 24$$\times$$ × improvement in throughput over a baseline serial decoder.

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Section: Final Decisionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Hardware Implementation of a Fixed-Point Decoder for Low-Density Lattice Codes

Srivastava

Gaudet

Mitran

2022

J Sign Process Syst

View full text Add to dashboard Cite

show abstract

“…The sparse (low-density) H-matrix that is used for the code construction also renders iterative decoding (also called message-passing) an efficient decoding method [7,8] similar to LDPC codes. However, the primary focus of LDLC research so far has been to demonstrate the theoretically achievable performance limits of LDLCs [7,[9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25]. Not much work has been done towards the hardware implementation of LDLC decoding.…”

Section: Introductionmentioning

confidence: 99%