eBSP: Managing NoC traffic for BSP workloads on the 16-core Adapteva Epiphany-III processor

Siddhartha, _; Kapre, Nachiket

doi:10.23919/date.2017.7926961

Cited by 1 publication

(1 citation statement)

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“…A number of other architectures consisting of large numbers of small cores communicating explicitly have been proposed over the years. Some of the most notable are: RAMP Blue [13] (which is able to run off-the-shelf parallel applications expressed in the Unified Parallel C framework), GRVI Phalanx [14] (which packs a remarkable 1,680 RISC-V cores on a single Xilinx XCVU9P FPGA), and Adapteva Epiphany [15,16] (which achieves high floating-point performance-per-watt). The trend in all these architectures is to support the partitioned global address space (PGAS) model of computation, where cores communicate by performing remote loads and stores to the memories of other cores.…”

Section: Related Workmentioning

confidence: 99%

Termination detection for fine-grained message-passing architectures

Naylor

Moore

Mokhov

et al. 2020

2020 IEEE 31st International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

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Barrier primitives provided by standard parallel programming APIs are the primary means by which applications implement global synchronisation. Typically these primitives are fully-committed to synchronisation in the sense that, once a barrier is entered, synchronisation is the only way out. For message-passing applications, this raises the question of what happens when a message arrives at a thread that already resides in a barrier. Without a satisfactory answer, barriers do not interact with message-passing in any useful way. In this paper, we propose a new refutable barrier primitive that combines with message-passing to form a simple, expressive, efficient, well-defined API. It has a clear semantics based on termination detection, and supports the development of both globally-synchronous and asynchronous parallel applications. To evaluate the new primitive, we implement it in a prototype large-scale message-passing machine with 49,152 RISC-V threads distributed over 48 FPGAs. We show that hardware support for the primitive leads to a highly-efficient implementation, capable of synchronisation rates that are an order-of-magnitude higher than what is achievable in software. Using the primitive, we implement synchronous and asynchronous versions of a range of applications, observing that each version can have significant advantages over the other, depending on the application. Therefore, a barrier primitive supporting both styles can greatly assist the development of parallel programs.

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Section: Related Workmentioning

confidence: 99%