Effect of pitch angle on modal propagation characteristics of an annular circular dielectric waveguide having helical windings on the inner and outer boundaries as claddings

Srivastava, S. K.; Pandey, Praveen C.; Singh, Umesh; Ojha, S. P.

doi:10.1002/mop.10315

Cited by 8 publications

(1 citation statement)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A novel idea about helically cladded elliptical waveguides has been suggested by Kumar et al [17]. Recently, Srivastava et al [18] studied annular waveguides with helical boundaries and discussed their propagation characteristics.…”

Section: Introductionmentioning

confidence: 99%

A theoretical analysis of the propagation characteristics of an annular circular waveguide with a helical winding as the inner cladding

Kumar

Srivastava

Ojha

2003

Micro & Optical Tech Letters

Self Cite

View full text Add to dashboard Cite

ing a drain current peak higher than I D,max have been ruled out. The optimum combinations of v gs and R S for a self-biased doubling device are represented by the left ends of the secondharmonic contour lines. In fact, at such points the required performance is achieved by fulfilling minimum RF input power and R S power dissipation, and maximum GS , thus preventing the minimum gate-source voltage to reach breakdown. The generated design chart has been used to select the source-bias resistor and the ac gate-source voltage level of the doubling device. The selected values are 30⍀ and 1.1 V, respectively, corresponding to a secondharmonic drain-current component of 23 mA. In particular, the gate-source voltage mean time value is Ϫ0.9 V; a minimum gate-source voltage of Ϫ2 V is therefore achieved, obtaining a good margin with respect to the breakdown of the device. The drain bias resistor has been computed using Eq. (2), in which V DD ϭ 4 V and the drain-source mean-time value is 2.5 V, corresponding to the middle point between the breakdown and knee region of the dc-output device characteristic. A drain resistor R D ϭ 20⍀ has been obtained.The buffer-device bias resistors have been selected to bias the active device for class A operation, in order to achieve high linearity.Circuit-matching networks have been designed to match the overall circuit and optimally load input and output terminals of the doubling device [5]. The output network has been designed to obtain a broadband match of the circuit output. The interstage network has been designed to match, under large signal operation, the output of the doubling device to the buffer input at secondharmonic frequency, and to load the output of the doubling device at fundamental frequency for maximum conversion gain. Finally, the input network is conjugately matched at fundamental frequency to the device input for maximum power transfer and at second harmonic for maximum conversion gain. In particular, a series resistance acting as an attenuator has been introduced to reduce the specified input-power level to the optimum-doubling level.The proposed doubler has been realized using 0.25-m GaAs PHEMT technology by UMS. The photograph of the circuit is shown in Figure 3, and the size of the chip is 2 ϫ 1.4 mm 2 . MEASUREMENT RESULTSMeasured doubler-conversion gain and the fundamental rejection for an input power of 11 dBm at 5.5 GHz are depicted in Figure 4. A conversion gain in excess of 1 dB and a fundamental rejection higher than 17 dB over a bandwidth of 27% is demonstrated. The circuit is fed with a power supply of 4 V and a drain-current mean-time value of 26 mA has been measured for the doubling device. In the absence of an RF input signal, a drain bias current of 18 mA and 30 mA have been measured for the doubling and buffer stages, respectively. CONCLUSIONA new approach for frequency doubler design that minimizes of the complexity of a system's control circuitry, has been proposed, and a design method for this type of circuit has been developed. The effectiveness ...

show abstract

Section: Introductionmentioning

confidence: 99%