Effect of via etching process and postclean treatment on via electrical performance

Abstract

INTRODUCTIONReliability in integrated circuit metallization has become a subject of importance as a result of the aggressive scaling of integrated circuit dimensions. The Semiconductor Industry Association's Technology Roadmap 2 estimates that, by the year 2005, the average number of metal levels will be 8-9. Operating at 105°C, the current density for the metal line will be 1.4 mA/cm 2 and the maximum current across a via will be 0.24 mA. This will push the reliability concerns to the limit, with contacts and vias becoming the weakest link in the multilevel interconnect system. However, there are many aspects of the reliability performance that are still not well understood. This is due in part to the many factors (microstructure, interfacial quality, stresses, film composition, physics of void nucleation and growth, thermal and current density dependencies, etc.) that influence reliability performance and to the inability to isolate the effect of these factors experimentally. 3,4 There are relatively few studies that address reliability issues for variations in via process design.Studies by Ting et al. 5 and Elliott 6 found that punch-through of the TiN antireflection coating (ARC) layer and nonconformal barrier deposition had deleterious effects on the W-plug lifetimes. Simulation results also showed that the peak stress under the W-plug was a sensitive function of the via geometry and the penetration of the W-plug through the TiN. 7 Besides this, increasing the thickness of TiN is effective in reducing the incidence of early failure by suppressing the stress-induced failures, as described by Walls. 4 The reliability of vias and interconnections between two metal lines are indeed complex phenomena because of the use of multiple materials and structures. The interfaces between dissimilar materials are hence the dominating factor in determining via performance.In view of the above factors, this study was aimed at evaluating the effect of various via etching schemes as well as the postclean treatment (PCT) on the via reliability performance. The stress-migration (SM) test was performed to investigate the temperature effect, while both the thermal and electrial factors were accounted for in the electromigration (EM) test. A schematic representation of the via etching approaches are shown in The effects of the via etching process as well as the postclean treatment (PCT) on the electrical performance of vias were studied. Stress-migration (SM) tests were carried out to investigate the effect of temperature. Both the thermal and electrical factors were assessed in the wafer-level conventional electromigration (EM) tests. Our results showed that the removal of the TiN antireflection coating (ARC) layer during via etch results in lower initial via resistance, higher resistance to SM, and longer EM lifetime. On the other hand, with additional PCT, the initial via resistance and SM resistance became worse. The C x F y residues 1 induced by the PCT step remain at the bottom of the via and degrade the interface properties....