Effects of simultaneous switching noise on the tapered buffer design

Ground bounce in digital VLSI circuits

“…The ground bounce causes an increase in the propagation delay of the output buffer and thus affects the optimal scaling factor in a series of tapered buffers [6]. As a result, the analytical results for the optimum scaling factor and the optimum number of output drivers proposed in [14] and [15] are no longer valid because they do not address the effects of non-ideal ground and power lines.…”

“…Therefore we expect that in the presence of noisy power/ground lines, the number of inverters decreases and the tapering factor increases. Another important observation is that the output transition times of first stages in a tapered buffer are not affected by ground bounce due to relatively small magnitudes of ground bounce during their switching transitions [6]. Using this observation, the total propagation delay in the presence of the ground bounce is obtained using Lemma 2.…”

“…Solving the above ODE for v n yields the following expression for the ground bounce in the interval in terms of t: (6) where:…”

“…Notice that a similar analysis may be performed for the power-supply bounce during the low-to-high output transitions. During the ground bounce analysis, only the effect of NMOS current on the ground bounce is considered i.e., the effect of PMOS currents is ignored [3], [6]. Fig.…”

“…While most prior works were concentrated on the case where all the drivers switch simultaneously, paper [4] considers the more realistic case where the drivers may switch at different times. The idea of considering the effects of ground bounce on the tapered buffer has been presented in a paper by Vemuru [6]. The author, however, does not provide the quantitative analysis required for designing the optimum number of drivers in the tapered buffer chain.…”