Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level

Abstract

Abstract. This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic simulator under development called HALOTIS. The implementation is aimed at efficiency and overall estimations, making it suitable to switching noise evaluation and current peaks localisation. Simulation results and comparison to HSPICE confirm the usefulness and efficiency of the approach.

Internode: internal node logic computational model

“…In this sense, we have observed that a mandatory way for improving accuracy is to consider different models in the dynamic behavior, depending on the different states associated to the logic behavior [11,12]. For example, the propagation delay of a gate can vary according to what input changes.…”