Efficient Circuit and an EM Model of an Electrostatic Discharge Generator

Yousaf, Jawad; Park, Myeongkoo; Lee, Ho-Sang; Youn, Jong-Chan; Lee, Daehee; Hwang, Chanseok; Nah, Wansoo

doi:10.1109/temc.2017.2787189

Cited by 15 publications

(9 citation statements)

References 15 publications

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“…The validation of the developed numerical model of ESD gun model [19,22] is performed prior to the conduction of DOE experimentation on the full-wave realistic models of DRAM memory modules. The numerical model is used to generate the standard ESD reference waveform and to predict the induced coupling at the victim point on 20 mm µ-strip line test PCB (DUT).…”

Section: Validation Of Estimation Of Induced Esd Noise Using 3d Em Modelmentioning

confidence: 99%

“…The simulation setup in Figure 3b is almost an exact replica of the system level ESD measurement setup in Figure 3a, as per the requirements of [23]. The detailed description of measurement setup and numerical models of Figure 2 can be found in [19,22]. The comparison of simulation and measured results of reference ESD waveforms is shown in Figure 4a for two input discharge voltage levels (+2 kV and +4 kV).…”

Section: Validation Of Estimation Of Induced Esd Noise Using 3d Em Modelmentioning

confidence: 99%

“…These include: failure analysis using susceptibility testing [5]; analysis of coupled ESD noise to DUT through time and frequency domain measurements [1,[10][11][12][13][14]; and full-wave EM simulation of DUT and ESD source [2,6,[15][16][17][18]. These reported techniques have limitations in terms of the requirement of the manufacturing of the DUT to perform susceptibility analysis [5], or the characterization of the coupled noise at victim positions for each different design configuration of the DUT [10][11][12][13][14]19].…”

Section: Introductionmentioning

confidence: 99%

“…Figure 1 shows the proposed DOE configurations based framework to identify the suitable design configuration of DUT for the reduction of soft-failure due to the coupled ESD noise. The validation of the designed 3D ESD gun model [19,22] for the full-wave EM simulations of memory modules is performed by comparing the injected current and induced voltage results for a microstrip line printed circuit board (PCB) in the complete IEC 61000-4-2 system level ESD setup environment [23]. After the validation of the made 3D EM numerical setup, microstrip line PCB is replaced with real models of the DDR3 and DDR4 memory modules for the current distribution analysis.…”

Section: Introductionmentioning

confidence: 99%

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Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules

et al. 2019

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This paper presents, for the first time, a comprehensive detailed design of experiment (DOE) based system level electrostatic discharge (ESD) coupling analysis of high-speed dynamic random access (DRAM) memory modules. The sensitive traces and planes on the high-speed DRAM modules (DDR3 and DDR4) against injected ESD noise are determined through full-wave numerical simulations of the memory modules using the developed 3D model of the ESD gun. The validity of the full-wave numerical setup is confirmed through measurements, prior to the DOE analysis. Besides, current distribution analysis of DRAMs, seven different DOE configurations based on the number of installed decoupling capacitors (decaps) and their values on memory modules, are analyzed. The findings of DOE analysis suggests that DDR4 is less susceptible (70–80 % less) to the coupled ESD noise compared to DDR3. In addition, the command address (CA) nets are most sensitive in both memory modules. The utilization of the maximum possible number of decaps covering low, medium and high frequency ranges, as well as separate power and ground layers in memory stack-up design, increase the robustness and immunity of memory modules for the transient ESD event. The suggested approach offers time-saving and financial advantages to high-speed memory community, with the robust design of the memory products at the design stage before the start of the production phase.

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Section: Validation Of Estimation Of Induced Esd Noise Using 3d Em Modelmentioning

confidence: 99%

Section: Validation Of Estimation Of Induced Esd Noise Using 3d Em Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules

et al. 2019

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“…In ESD measurement, it is difficult to precisely determine the current paths in the DUT, while a pass or fail evaluation can be conducted. ESD gun models have been proposed for ESD standards at the simulation level [9]- [11], and fullwave 3D electromagnetic field simulation has been conducted for a PCB-level ESD analysis method [12]- [14]. A method for observing ESD waveforms when ESD enters through the input/output (I/O) pins of ICs has also been devised [15].…”

Section: Introductionmentioning

confidence: 99%

Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging

Wadatsumi

Kawai

Hasegawa

et al. 2023

IEICE Trans. Electron.

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This paper presents on-chip characterization of electrostatic discharge (ESD) impacts applied on the Si-substrate backside of a flip-chip mounted integrated circuit (FC-IC) chip. An FC-IC chip has an open backside and there is a threat of reliability problems and malfunctions caused by the backside ESD. We prepared a test FC-IC chip and measured Si-substrate voltage fluctuations on its frontside by an on-chip monitor (OCM) circuit. The voltage surges as large as 200 mV were observed on the frontside when a 200-V ESD gun was irradiated through a 5 kΩ contact resistor on the backside of a 350 µm thick Si substrate. The distribution of voltage heights was experimentally measured at 20 on-chip locations among thinned Si substrates up to 40 µm, and also explained in full-system level simulation of backside ESD impacts with the equivalent models of ESD-gun operation and FC-IC chip assembly.

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Rapid characterization of efficient system level ESD protection strategy using coupling transfer function

Yousaf

Nah

Majali

et al. 2021

Microelectronics Journal

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Efficient Circuit and an EM Model of an Electrostatic Discharge Generator

Cited by 15 publications

References 15 publications

Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules

Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules

Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging

Rapid characterization of efficient system level ESD protection strategy using coupling transfer function

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