Efficient design space exploration in PICO

Abraham, Santosh G.; Rau, B. Ramakrishna

doi:10.1145/354880.354891

Cited by 25 publications

(13 citation statements)

References 13 publications

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“…A basic measure of a soft core's size on an FPGA is the number of utilized lookup tables (LUTs) 1 . However, a soft core may also utilize hard-core FPGA resources, such as hard-core multipliers or block RAMs.…”

Section: Soft-core Framework and Exploration Methodsmentioning

confidence: 99%

“…Note that the equivalent LUT concept is essentially a cost function that combines three terms by normalizing them and weighing 1 We originally utilized configurable logic blocks (CLBs) as a measure of size, but MicroBlaze designers at Xilinx informed us that LUTs are a more accurate and useful measure. them equally.…”

Section: Soft-core Framework and Exploration Methodsmentioning

confidence: 99%

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Application-specific customization of parameterized FPGA soft-core processors

Sheldon¹,

Kumar²,

Lysecky³

et al. 2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are parameterized to support application-specific customization, wherein pre-defined units, such as a multiplication unit or floating-point unit, may be included in the microprocessor architecture to speed up software execution at the expense of increased size. We introduce a methodology for fast applicationspecific customization of a parameterized FPGA soft core, using synthesis and execution to obtain size and performance data in order to create a tool that can be used across a variety of tool platforms and FPGA devices. As synthesizing a soft core takes tens of minutes, developing heuristics that execute in an acceptable time of an hour or two, yet find near-optimal results, is a challenge. We consider two approaches, one using a traditional CAD approach that does an initial characterization using synthesis to create an abstract problem model and then explores the solution space using a knapsack algorithm, and the other using a synthesisin-the-loop exploration approach. We compare approaches for a variety of design constraints, on 11 EEMBC benchmarks, using an actual Xilinx soft-core processor, and for two different commercial Xilinx FPGA devices. Our results show that the approaches can generate a customized configuration exhibiting roughly 2x speedups over a base soft core, reaching within 4% of optimal in about 1.5 hours, including complete synthesis of the soft-core onto the FPGA, compared to over 11 hours for exhaustive search. Our results also show that including synthesisin-the-loop, compared to a traditional CAD approach, improved speedups by an average of 20% when size constraints were tight. The approaches may also be applicable to soft-core processors targeted to ASICs in addition to FPGAs.

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Section: Soft-core Framework and Exploration Methodsmentioning

confidence: 99%

Section: Soft-core Framework and Exploration Methodsmentioning

confidence: 99%

Application-specific customization of parameterized FPGA soft-core processors

Sheldon¹,

Kumar²,

Lysecky³

et al. 2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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show abstract

“…For example, ShiftQ [2], the nonprogrammable accelerator (NPA) for program-in-computer-out [1] (PICO) systems enables the user to quickly find an optimum hardware solution.…”

Section: Comparison With Other Approachesmentioning

confidence: 99%

ASC: a stream compiler for computing with FPGAs

Mencer

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-A stream compiler (ASC) for computing with field programmable gate arrays (FPGAs) emerges from the ambition to bridge the hardware-design productivity gap where the number of available transistors grows more rapidly than the productivity of very large scale integration (VLSI) and FPGA computer-aideddesign (CAD) tools. ASC addresses this problem with a softwarelike programming interface to hardware design (FPGAs) while keeping the performance of hand-designed circuits at the same time. ASC improves productivity by letting the programmer optimize the implementation on the algorithm level, the architecture level, the arithmetic level, and the gate level, all within the same C++ program.The increased productivity of ASC is applied to the hardware acceleration of a wide range of applications. Traditionally, hardware accelerators are tediously handcrafted to achieve top performance. ASC simplifies design-space exploration of hardware accelerators by transforming the hardware-design task into a software-design process, using only "GNU compiler collection (GCC)" and "make" to obtain a hardware netlist. From experience, the hardware-design productivity and ease of use are close to pure software development.This

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“…With the advent of core-based design, much recent research and commercial tools have focused on tuning the microprocessor instruction set to one fixed program [1][3] [4] [14][15] [21]. In our work, we focus on the complementary problem of tuning the memory hierarchy to a fixed program.…”

Section: Introductionmentioning

confidence: 99%