Efficient FPGA Implementation of Address Generator for WiMAX Deinterleaver

Upadhyaya, Bijoy Kumar; Sanyal, Sugata

doi:10.1109/tcsii.2013.2268372

Cited by 9 publications

(12 citation statements)

References 7 publications

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“…In this case, the MUX M4 selects the row counter output incremented by 1 based on MOD_row[1] = '0' else decrement by 2. In our design, we have reduced the size of the MUXs compared with the logic in [19] by having special kind of select signal. Moreover, the control signals are not generated externally, but generated internally from encoded binary values.…”

Section: Proposed Reconfigurable Address Generator Architecturementioning

confidence: 99%

“…Therefore, the proposed MOD circuit for row and column, eliminates the need for two ROMs of dimension 16 × 3-bit and 64 × 3-bit in [19] to store the MOD values for 16-QAM and 64-QAM respectively, which yields a substantial amount of reduction in resources and improvement in performance.…”

Section: Working Of Mod_rowmentioning

confidence: 99%

“…Zhang et al [18] had presented, a low complexity architecture for interleaver/ deinterleaver suitable for MIMO application in 802.11a/g/n wireless LAN. Upadhyaya et al [19] have designed and implemented separate hardware for QPSK, 16-QAM, and 64-QAM address generator on FPGA for WiMAX channel deinterleaver.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios

Venkatachalam¹,

Lakshminarayanan²,

Sellathurai³

2016

IET Computers & Digital Techniques

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Developing a reconfigurable transceiver to support multiple protocols seamlessly and efficiently is an extremely tough task. Wireless standards such as wireless local area network (IEEE 802.11a/g) and WiMAX (IEEE 802.16e) incorporate block interleaving technique to overcome the occurrence of burst errors during transmission. Field Programmable Gate Array (FPGA) implementation of floor and modulus (MOD) functions to perform the two step permutation for attaining the new index is quite complex. In this study, the authors propose a low complexity and area efficient reconfigurable architecture for multimode interleaver address generator to support multiple wireless standards. In addition, a novel MOD_row and MOD_column circuit are proposed to compute MOD function for row and column counter values, respectively. The proposed address generation circuitry supports BPSK, QPSK, 16-QAM and 64-QAM modulation schemes under all possible code rates. The reconfigurable address generator for various block size and modulation scheme are implemented on Xilinx Spartan XC3S400 FPGA and the functionalities are verified through simulation. The synthesis results of the proposed design shows a reduction of 60% in resource utilisation and an improvement of 46% in operating frequency over the existing approaches.

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Section: Proposed Reconfigurable Address Generator Architecturementioning

confidence: 99%

Section: Working Of Mod_rowmentioning

confidence: 99%

See 1 more Smart Citation

Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios

Venkatachalam¹,

Lakshminarayanan²,

Sellathurai³

2016

IET Computers & Digital Techniques

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“…In the proposed design the deinterleaving is done based upon two mathematical equations which are described below [8].…”

Section: B Proposed Designmentioning

confidence: 99%

High speed address generating design for the dynamic modulation scheme supportive WiMAX deinterleaver

Mohan

Cheriyan

2014

2014 Annual International Conference on Emerging Research Areas: Magnetics, Machines and Drives (AICERA/iCMMD)

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In this paper a new high speed address generator for the dynamic modulation scheme supportive WiMAX deinterleaver design is proposed. The WiMAX can be both fixed and mobile, in this work the mobile WiMAX is given more importance. The mobile WiMAX uses interleaving and deinterleaving techniques in its transreceiver for eliminating the transmission errors. The WiMAX supports QPSK, 16-QAM and 64-QAM modulation schemes for establishing a connection between subscriber and base stations. Deinterleaver has to produce the addresses for these different modulation schemes by performing the inverse operation of interleaving. The address generator in the deinterleaver hinders the performance of the receiver section of the WiMAX system so it has to be optimized to improve the overall performance. In this paper a new ASIC based design has been proposed for the address generator and the design is been modelled in VHDL. Keywords-WiMAX (Worldwide interoperatability for microwave access); FEC (Forward error correction); ASIC; deinterleaving; VHDLI.

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“…The deinterleaving takes place after de-mapping received information by two permutation which is stated as equations (3) and (4) [9].…”

Section: B Proposed New Correlationmentioning

confidence: 99%

Proficient receptive combined address generator archetypal for WiMAX and WiFi deinterleaver precinct

Mohan

Cheriyan

2014

2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)

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In this paper a combined responsive address generator archetypal for WiMAX and WiFi deinterleaver unit aimed for using in wireless broadband system is being proposed. Deinterleaver is used in conjunction with forward error correction unit for eliminating and correcting different transmission errors which occurs when signals are transmitted from base station to subscriber station. Address generator unit plays a vital role in deciding the overall performance of deinterleaver section. A novel proficient address generator supporting varying modulation schemes such as QPS K, 16-QAM and 64-QAM for both WiMAX and WiFi systems is being proposed in this paper. By combining the address generator unit we can use this design to generate deinterleaver addresses for both WiMAX and WiFi enabled scenarios with ease. The FPGA and 130 nm standard library AS IC results are studied by modelling the design in VHDL. Keywords-transmission errors; WiMAX (Worldwide interoperability for microwave access); WiFi (Wireless Fidelity); FPGA; deinterleaver, (BER) Bit-Error-Rate I.978-1-4799-4190-2/14/$31.00 ©2014 IEEE

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Efficient FPGA Implementation of Address Generator for WiMAX Deinterleaver

Cited by 9 publications

References 7 publications

Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios

Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios

High speed address generating design for the dynamic modulation scheme supportive WiMAX deinterleaver

Proficient receptive combined address generator archetypal for WiMAX and WiFi deinterleaver precinct

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