Efficient software synthesis of dynamic dataflow programs

Yviquel, Hervé; Sanchez, Alexandre; Jääskeläinen, Pekka; Takala, Jarmo; Raulet, Mickaël; Casseau, Emmanuel

doi:10.1109/icassp.2014.6854551

Cited by 4 publications

(5 citation statements)

References 17 publications

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“…This approach targets application-specific platforms which makes it much less flexible than our new approach. Outside of the architecture side, our software synthesis which is also applicable on general-purpose processors has significantly improved the performance: We observed an improvement of more than 100% of the decoding frame-rates over previous implementations (at equal frequency) [34].…”

Section: Related Workmentioning

confidence: 88%

“…For that reason, this section presents a set of advanced software synthesis techniques based on preliminary work [34] that enhance the performance of the implementation of dynamic dataflow programs using their specific properties and the flexibility of software systems.…”

Section: Software Synthesis Of Dynamic Dataflow Programsmentioning

confidence: 99%

“…This architecture model is based on distributed memory organization and exposed-datapath core architecture so as to improve the global efficiency of the platform (power consumption and decoding framerate). -We present a set of advanced software synthesis techniques, based on preliminary work [34], that enhance the performance of implementations of dynamic dataflow programs using their specific properties and the flexibility of software systems over hardware systems.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs

Yviquel

Sanchez²,

Jääskeläinen³

et al. 2014

J Sign Process Syst

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Multimedia applications and embedded platforms are both becoming very complex in order to improve user experience. Thus, multimedia developers need high-level methods to automate time-consuming and error-prone tasks. Dynamic dataflow modeling is attractive to describe complex applications, such as video codecs, at a high level of abstraction. This paper presents a dataflow-based design approach to implement video codecs on embedded multi-core platforms. First, we introduce a custom architecture model to design lowpower multi-core chips based on distributed memory and Transport-Triggered Architecture processor cores. Then, we describe software synthesis techniques to improve dynamic dataflow implementations. This methodology has been implemented into open-source tools and demonstrated on video decoders based on the MPEG-4 Visual standard and the new High Efficiency Video Coding standard. The simulations achieve real-time decoding (40FPS) of high definition (720P) MPEG-4 Visual video sequences on a custom multi-core platformWe would like to thank the organizations which have partially funded this work such as the Center for International Mobility (CIMO) and the Academy of Finland (funding decision 253087). We would also give special thanks to the Orcc and TCE communities as a whole for actively participating in the development of the tools which offers solid basements to this work. clocked at 1Ghz, which is an improvement of more than 100% over previously proposed implementations.

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Section: Related Workmentioning

confidence: 88%

Section: Software Synthesis Of Dynamic Dataflow Programsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs

Yviquel

Sanchez²,

Jääskeläinen³

et al. 2014

J Sign Process Syst

View full text Add to dashboard Cite

show abstract

“…Orcc is a complete Eclipsebased IDE that embeds two editors for both actor and network programming, a functional simulator and a dedicated multi-target compiler. The compiler is able to translate the RVC-based description of an application into an equivalent description in both hardware [5,6] and software languages [7,8] for various platforms (FPGA, GPP, DSP, etc). A specific compiler back-end has been written to tackle each configuration case such as presented in Figure 2.…”

Section: Reconfigurable Video Codingmentioning

confidence: 99%

On the Development and Optimization of HEVC Video Decoders Using High-Level Dataflow Modeling

Jerbi

Yviquel

Sanchez

et al. 2016

J Sign Process Syst

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International audienceWith the emergence of the High Efficiency Video Coding (HEVC) standard, a dataflow description of the decoder part was developed as part of the MPEG-B standard. This dataflow description presented modest framerate results which led us to propose methodolo-gies to improve the performance. In this paper, we introduce architectural improvements by exposing more parallelism using YUV and frame-based parallel decoding. We also present platform optimizations based on the use of SIMD functions and cache efficient FIFOs. Results show an average acceleration factor of 5.8 in the decoding framerate over the reference architecture

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“…An important problem in the development of dataflowbased design tools is the automated synthesis of software from dataflow representations. Many software synthesis environments for dataflow environments have been presented in the literature (e.g., see [13,31,33,34,42,48]), and dataflow-based software synthesis continues to be an active area of research in the embedded systems, electronic design automation, and signal processing communities. In this paper, we develop new software synthesis techniques for dataflow-based design and implementation of signal processing systems.…”

Section: Introductionmentioning

confidence: 99%

Software synthesis from dataflow schedule graphs

Lee

Raina

et al. 2021

SN Appl. Sci.

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The dataflow-model of computation is widely used in design and implementation of signal processing systems. In dataflow-based design processes, scheduling—the assignment and coordination of computational modules across processing resources—is a critical task that affects practical measures of performance, including latency, throughput, energy consumption, and memory requirements. Dataflow schedule graphs (DSGs) provide a formal abstraction for representing schedules in dataflow-based design processes. The DSG abstraction allows designers to model a schedule as a separate dataflow graph, thereby providing a formal, abstract (platform- and language-independent) representation for the schedule. In this paper, we introduce a design methodology that is based on explicit specifications of application graphs and schedules as cooperating dataflow models. We also develop new techniques and tools for automatically synthesizing efficient implementations on multicore platforms from these coupled application and schedule models. We demonstrate the proposed methodology and synthesis techniques through a case study involving real-time detection of people and vehicles using acoustic and seismic sensors.

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Efficient software synthesis of dynamic dataflow programs

Cited by 4 publications

References 17 publications

Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs

Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs

On the Development and Optimization of HEVC Video Decoders Using High-Level Dataflow Modeling

Software synthesis from dataflow schedule graphs

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