Efficient verification of real-time systems: compact data structure and state-space reduction

Larsen, Kim Guldstrand; Larsson, Fredrik; Pettersson, Paul; Yi, Wang

doi:10.1109/real.1997.641265

Cited by 108 publications

(117 citation statements)

References 12 publications

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“…As described in [LLPY97], constraints as symbolic representations of states are used in uppaal, a verification tool for timed systems [LPY97]. It seems that, for reasons of syntax, it is not possible to verify safety for our examples in the current version of uppaal (but possibly in an extension).…”

Section: Related Workmentioning

confidence: 99%

Model Checking in CLP

Delzanno

Podelski

1999

Tools and Algorithms for the Construction and Analysis of Systems

106

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Abstract. We show that Constraint Logic Programming (CLP) can serve as a conceptual basis and as a practical implementation platform for the model checking of infinite-state systems. Our contributions are:(1) a semantics-preserving translation of concurrent systems into CLP programs, (2) a method for verifying safety and liveness properties on the CLP programs produced by the translation. We have implemented the method in a CLP system and verified well-known examples of infinitestate programs over integers, using here linear constraints as opposed to Presburger arithmetic as in previous solutions.

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Section: Related Workmentioning

confidence: 99%

Model Checking in CLP

Delzanno

Podelski

1999

Tools and Algorithms for the Construction and Analysis of Systems

106

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“…When analyzing the plant models we have used the compact data-structure for constraints [LLPY97], the control-structure reduction [LLPY97], and a recently implemented version of the (in-)active clock reduction [DT98].…”

Section: Resultsmentioning

confidence: 99%

Guided Synthesis of Control Programs for a Batch Plant using UPPAAL

Hune¹,

Larsen²,

Pettersson³

2000

BRICS

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Abstract. In this paper we address the problem of scheduling and synthesizing distributed control programs for a batch production plant. We use a timed automata model of the batch plant and the verification tool Uppaal to solve the scheduling problem. In modeling the plant, we aim at a level of abstraction which is sufficiently accurate in order that synthesis of control programs from generated timed traces is possible. Consequently, the models quickly become too detailed and complicated for immediate automatic synthesis. In fact, only models of plants producing two batches can be analyzed directly! To overcome this problem, we present a general method allowing the user to guide the model-checker according to heuristically chosen strategies. The guidance is specified by augmenting the model with additional guidance variables and by decorating transitions with extra guards on these. Applying this method have made synthesis of control programs feasible for a plant producing as many as 60 batches. The synthesized control programs have been executed in a physical plant. Besides proving useful in validating the plant model and in finding some modeling errors, we view this final step as the ultimate litmus test of our methodology's ability to generate executable (and executing) code from basic plant models.

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“…Model checking with time leads to real-time model checking [14,71,72]. The properties that can be checked with [mc]square are not restricted to invariants but can be arbitrary CTL formulas (for restrictions see Sect.…”

Section: Model Checking Machine Codementioning

confidence: 99%

“…Estes [82] preserves discrete time, but it faces the state-explosion problem when checking bigger programs. There are model checkers that do real-time model checking such as HyTech [58], KRONOS [130], and Uppaal [14,71,72].…”

Section: Related Workmentioning

confidence: 99%

Model Checking Software

Donaldson¹,

Parker²

2012

Lecture Notes in Computer Science

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Software of microcontrollers is getting more and more complex. It is mandatory to extensively analyze their software as errors can lead to severe failures or cause high costs. Model checking is a formal method used to verify whether a system satisfies certain properties.This thesis describes a new approach for model checking software for microcontrollers. In this approach, assembly code is used for model checking instead of an intermediate representation such as C code.The development of [mc]square, which is a microcontroller assembly code model checker implementing this approach, is detailed.[mc]square has a modular architecture to cope with the hardware dependency of this approach. The single steps of the model checking process are divided into separate packages. The creation of the states is conducted by a specific simulator, which is the only hardware-dependent package. Within the simulator, the different microcontrollers are modeled accurately.This work describes the modeling of the ATMEL ATmega16 microcontroller and details implemented abstraction techniques, which are used to tackle the stateexplosion problem. These abstraction techniques include lazy interrupt evaluation, lazy stack evaluation, delayed nondeterminism, dead variable reduction, and path reduction. Delayed nondeterminism introduces symbolic states, which represent a set of states, into [mc]square while still explicit model checking techniques are used. Thus, we successfully combined explicit and symbolic model checking techniques.A formal model of the simulator, which we developed to prove the correctness of abstraction techniques, is described. In this work, the formal model is used to show the correctness of delayed nondeterminism.To show the applicability of the approach, two case studies are described. In these case studies, we used programs of different sizes. All these programs were created by students in lab courses, during diploma theses, or in exercises without the intention to use them for model checking.

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Efficient verification of real-time systems: compact data structure and state-space reduction

Cited by 108 publications

References 12 publications

Model Checking in CLP

Model Checking in CLP

Guided Synthesis of Control Programs for a Batch Plant using UPPAAL

Model Checking Software

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