Abstract:Considerable efforts have been devoted to the design of low-power digital electronics. However, after decades of improvements and maturation, CMOS technology could face an efficiency ceiling. This is due to the trade-off between leakage and conduction losses inherent to transistors. Consequently, the lowest dissipation per operation remains nowadays few decades higher than the theoretical Landauer's limit (3 zJ at 300 K). Adiabatic CMOS architectures are good candidates for reducing the dynamic losses. But adi… Show more
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