Electronic Implementation of Multirate Sigma-Delta Modulators Using CMOS Technologies

Abstract

Multirating has been recently proposed to reduce the frequency rate of the first integrator(s) of a single-loop, or the first stage(s) of a cascade, Sigma-Delta modulator (SDM). This is a promising technique for the design of high speed, low-power modulators, as the first integrator (or stage) in the chain primarily determines the performances of the modulator, as well as its power consumption. This paper presents the first implementation of a 2nd-order multirate SDM, showing different circuit solutions. The experimental results obtained with a prototype in a standard 0.6 µm CMOS technology shows that different clock rates can be selected for each integrator of a SDM.