Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems

Banerjee, K.; Lin, Sung-Chyr; Srivastava, N.

doi:10.1109/aspdac.2006.1594686

Cited by 3 publications

(8 citation statements)

References 38 publications

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“…High temperatures can cause reliability problems in a VLSI circuit since they exacerbate electromigration in metal wires [7], hot-carrier effects in transistors, and thermal-stress-related gateoxide breakdown in transistors [8]. These problems get more severe with transistor scaling.…”

Section: Impact Of Elevated Temperatures On Circuit Performance Mmentioning

confidence: 99%

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TABS: Temperature-Aware Layout-Driven Behavioral Synthesis

Krishnan

Katkoori

2010

IEEE Trans. VLSI Syst.

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With rising power densities in modern VLSI circuits, thermal effects are becoming important in the design of ICs. Elevated chip temperatures have an adverse impact on performance, reliability, power consumption, and cooling costs. To ensure adequate thermal management, all phases of the design flow must account for thermal effects on their design decisions. We present a two-stage simulated annealing-based high-level synthesis technique that combines power minimization with temperature-aware scheduling, binding, and floorplanning. In our technique, the first stage of the simulated annealing algorithm creates a low-power solution, which is then iteratively improved by the second stage to minimize estimated on-chip peak temperature using accurate module-level temperature estimation. We show that minimizing average power alone does not guarantee minimal peak temperatures. However, our approach consistently finds solutions that have lower on-chip peak temperatures and uniform on-chip temperature distributions, compared to a traditional low-power synthesis methodology that minimizes average power. Experiments show that our method reduces peak temperatures on average by 12% and up to 16%, compared to a traditional low-power synthesis algorithm that minimizes average power. These improvements in chip-level temperature distributions are achieved with a modest increase in chip area of under 15% on average.Index Terms-Behavioral synthesis, high-level synthesis (HLS), multistage simulated annealing, on-chip temperature variations, thermal hot spots, thermal management.

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Section: Impact Of Elevated Temperatures On Circuit Performance Mmentioning

confidence: 99%

“…Temperature-related failures currently account for more than 50% of all IC failures [4]. Thermal issues will have a much greater impact on the reliability and performance of ICs in future nanometer CMOS technologies due to increasing variability of key process parameters [8].…”

Section: Impact Of Elevated Temperatures On Circuit Performance Mmentioning

confidence: 99%

TABS: Temperature-Aware Layout-Driven Behavioral Synthesis

Krishnan

Katkoori

2010

IEEE Trans. VLSI Syst.

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“…An MWCNT consists of several shells. The number of shells is determined by D outer , which is based on (2). Each shell has its own d i , λ, andÑ chan/shell , which can be derived from D outer .…”

Section: Conductance Of Mixed Cnt Bundlementioning

confidence: 99%

“…In order to use the mixed CNT bundles, models that can accurately characterize their behaviors need to be created. Several SWCNT resistance or conductance models have been proposed in the literature [2]- [6]. However, the MWCNT models that are important for analyzing mixed CNT bundles are not fully explored.…”

Section: Introductionmentioning

confidence: 99%

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Analyzing Conductance of Mixed Carbon-Nanotube Bundles for Interconnect Applications

Haruehanroengra

Wang

2007

IEEE Electron Device Lett.

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The carbon-nanotube (CNT) bundle is a potential candidate for deep-nanometer-interconnect applications due to its superior conductivity and current-carrying capabilities. A CNT bundle is generally a mixture of single-wall and multiwall CNTs (SWCNTs and MWCNTs) and has not been fully explored in previous studies. This letter introduces a diameter-dependent model to analyze the conductance of both SWCNTs and MWCNTs. Using this model, the conductance performance of the mixed CNT bundles is analyzed, and the estimation is consistent with the corresponding experimental result. This letter also demonstrates that the mixed CNT bundles can provide two to five times conductance improvement over copper by selecting the suitable parameters such as bundle width, tube density, and metallic tube ratio.

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Lattice Boltzmann method with effective correction of phonon properties for nano/microscale heat transfer

Huang¹,

Hou²,

Ge³

2022

Phys. Scr.

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The significant self-heating effect severely restricts the performance and reliability of nano-electronic devices. Accordingly, it is very important to understand the process and mechanism of nano/microscale heat transfer for thermal management and thermal design of devices. In this work, we propose a new Lattice Boltzmann Method (LBM) scheme with effective correction of phonon mean free path (MFP) and relaxation time to study phonon heat transfer in silicon thin films and silicon medium with defects, where the correction factor is dependent on the lattice structure of LBM. The transformation analysis of phonon transfer mechanism at different scales shows that the size effect of cross-plane thermal conductivity is more remarkable than that of in-plane thermal conductivity. And the thermal conductivity of silicon medium with defects decreases exponentially as defect density increases. The proposed new LBM scheme can generate more accurate results than the traditional ones in the heat conduction simulations of different nano/microscale structures.

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Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems

Cited by 3 publications

References 38 publications

TABS: Temperature-Aware Layout-Driven Behavioral Synthesis

TABS: Temperature-Aware Layout-Driven Behavioral Synthesis

Analyzing Conductance of Mixed Carbon-Nanotube Bundles for Interconnect Applications

Lattice Boltzmann method with effective correction of phonon properties for nano/microscale heat transfer

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