Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering

Barth, J.; Dreibelbis, J.; Nelson, Erik; Anand, D.; Pomichter, G.; Jakobsen, P.; Nelms, M.; Leach, Janice; Belansek, G.

doi:10.1147/rd.466.0675

Cited by 25 publications

(8 citation statements)

References 9 publications

(9 reference statements)

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“…Dynamic random-access memory1 is a type of memory that stores each bit of data in a separate capacitor within an integrated circuit. However, it has to be refreshed periodically.…”

mentioning

confidence: 99%

A chiral-based magnetic memory device without a permanent magnet

et al. 2013

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Several technologies are currently in use for computer memory devices. However, there is a need for a universal memory device that has high density, high speed and low power requirements. To this end, various types of magnetic-based technologies with a permanent magnet have been proposed. Recent charge-transfer studies indicate that chiral molecules act as an efficient spin filter. Here we utilize this effect to achieve a proof of concept for a new type of chiral-based magnetic-based Si-compatible universal memory device without a permanent magnet. More specifically, we use spin-selective charge transfer through a self-assembled monolayer of polyalanine to magnetize a Ni layer. This magnitude of magnetization corresponds to applying an external magnetic field of 0.4 T to the Ni layer. The readout is achieved using low currents. The presented technology has the potential to overcome the limitations of other magnetic-based memory technologies to allow fabricating inexpensive, high-density universal memory-on-chip devices.

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“…Dynamic random-access memory1 is a type of memory that stores each bit of data in a separate capacitor within an integrated circuit. However, it has to be refreshed periodically.…”

mentioning

confidence: 99%

A chiral-based magnetic memory device without a permanent magnet

et al. 2013

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“…In addition, the direct tunneling current also may occur because the voltage across the intersection of drain and gate is equal to . Hence, the total leakage current of the switch transistor for a given temperature can be expressed as (13) where and is the tunneling area of direct tunneling and BTBT.…”

Section: ) Gate Tunneling Currentmentioning

confidence: 99%

Testing Methodology of Embedded DRAMs

Yang

Chang

Chao

et al. 2012

IEEE Trans. VLSI Syst.

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The embedded-DRAM (eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core.

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“…Besides SRAM, the IBM CU-11 library also offers embedded DRAM macros [5] in multiples of 128 KB. Although embedded DRAM access time is much higher than SRAM, it offers three times more density.…”

Section: L3 Cachementioning

confidence: 99%

Blue Gene/L compute chip: Memory and Ethernet subsystem

Ohmacht¹,

Bergamaschi²,

Bhattacharya³

et al. 2005

IBM J. Res. & Dev.

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The Blue Genet/L compute chip is a dual-processor system-on-a-chip capable of delivering an arithmetic peak performance of 5.6 gigaflops. To match the memory speed to the high compute performance, the system implements an aggressive three-level on-chip cache hierarchy. The implemented hierarchy offers high bandwidth and integrated prefetching on cache hierarchy levels 2 and 3 (L2 and L3) to reduce memory access time. A Gigabit Ethernet interface driven by direct memory access (DMA) is integrated in the cache hierarchy, requiring only an external physical link layer chip to connect to the media. The integrated L3 cache stores a total of 4 MB of data, using multibank embedded dynamic random access memory (DRAM). The 1,024-bit-wide data port of the embedded DRAM provides 22.4 GB/s bandwidth to serve the speculative prefetching demands of the two processor cores and the Gigabit Ethernet DMA engine. To reduce hardware overhead due to cache coherence intervention requests, memory coherence is maintained by software. This is particularly efficient for regular highly parallel applications with partitionable working sets. The system further integrates an on-chip double-data-rate (DDR) DRAM controller for direct attachment of main memory modules to optimize overall memory performance and cost. For booting the system and low-latency interprocessor communication and synchronization, a 16-KB static random access memory (SRAM) and hardware locks have been added to the design. IBM J. RES. & DEV. VOL. 49 NO. 2/3 MARCH/MAY 2005 M. OHMACHT ET AL.

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Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering

Cited by 25 publications

References 9 publications

A chiral-based magnetic memory device without a permanent magnet

A chiral-based magnetic memory device without a permanent magnet

Testing Methodology of Embedded DRAMs

Blue Gene/L compute chip: Memory and Ethernet subsystem

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