Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview

Abstract

We provide an overview of selected crypto-hardware devices, with a special reference to the lightweight electronic implementation of encryption/decryption schemes, hash functions, and true random number generators. In detail, we discuss the hardware implementation of the chief algorithms used in private-key cryptography, public-key cryptography, and hash functions, discussing some important security issues in electronic crypto-devices, related to side-channel attacks (SCAs), fault injection attacks, and the corresponding design countermeasures that can be taken. Finally, we present an overview about the hardware implementation of true random number generators, discussing the chief electronic sources of randomness and the types of post-processing techniques used to improve the statistical characteristics of the generated random sequences.A. J. ACOSTA, T. ADDABBO AND E. TENA-SÁNCHEZ resource consumption. This matter sets the point for the lightweight cryptography, that is, the subfield of cryptography aiming to provide solutions tailored for resource-constrained devices.According to Elsevier Scopus, the largest database of research peer-reviewed literature, since 2010, about 40k documents are returned if searching the keyword 'cryptography' [6]. A huge subset of these papers deals with conceptual, algorithmic, software, hardware solutions that may be taken into account in lightweight cryptography. In the face of such a vast literature, in this work, we provide a brief overview of selected crypto-hardware devices, with a special reference to the lightweight electronic implementation of encryption/decryption schemes, hash functions, and true random number generators (TRNGs).This paper is organized as in the following. In Section 2, we introduce some terminology and present an overview of the hardware implementation of the chief algorithms used in private-key cryptography, public-key cryptography (PKC), and hash functions. In Sections 3 and 4, we introduce some important security concerns about electronic crypto-devices, discussing SCAs, fault injection attacks, and the corresponding countermeasures that can be taken in the hardware design. Finally, Sections 5-8 are devised to provide an overview about the electronic implementation of TRNGs. In detail, in Sections 5 and 6, we discuss about security flaws, statistical defects, and predictability of TRNGs, presenting the chief sources of randomness used nowadays for their hardware implementation. In Sections 7 and 8, we discuss an overview of the different post-processing techniques aimed to improve the statistical characteristics of the generated random sequences and the evaluation methods used to assess the reliability of cryptographic TRNGs. Conclusion and References close the paper. CRYPTOGRAPHIC ALGORITHMSCryptographic algorithms aim to convert secret data into an unreadable code for non authorized persons, protecting secret information from theft or alteration and also enabling authentication. For better understanding, in the next sections, we define the following...

Self‐tunable chaotic true random bit generator in current‐mode CMOS circuit with nonlinear distortion analysis

“…13 For the sake of completeness, we report that the collected sequences passed all the NIST cryptographic statistical test for random sources, 25 applying a minimal postprocessing, like the 16-bit lowcomplexity methods proposed in Addabbo et al 26 If the latter result was obtained for the specific implemented chip prototype, for a safe secure solution to be used in cryptographic application, the designer should tailor the postprocessing, taking into account a worst-case design, which for the solution discussed in this work can be evaluated by investigating the introduced dynamical models, considering both the digital resolution of the parametric tuning and random/systematic noise transient analysis from analog circuit simulation (eg, due to electronic noise and switching activity), in different operational conditions (supply voltage, and temperature). It has to be understood that this work deals with the design of high-quality low-complexity raw TRBG chaotic cores, that in practical application must be followed by a sequence postprocessing to mask or remove residual statistical biasing with scrambling and compression.…”

“…[1][2][3][4][5][6][7][8][9][10][11][12] If the former can be obtained resorting to digital circuits, 9,13 chaotic TRBGs are devised to issue random numbers by exploiting the measurement of truly chaotic physical processes, implemented in analog circuits. [1][2][3][4][5][6][7][8][9][10][11][12] If the former can be obtained resorting to digital circuits, 9,13 chaotic TRBGs are devised to issue random numbers by exploiting the measurement of truly chaotic physical processes, implemented in analog circuits.…”

“…Among the set of autonomous dynamical systems, piecewise linear chaotic maps represent the subset of chaotic systems for which ergodic theory provides the best theoretical knowledge investigating the link between the map parameters and the information generation mechanism exploited to issue random numbers. 13 Referring to the simplified block diagram shown in Figure 1, in this paper, we discuss the low-complexity IC design of a TRBG with parametric self-tuning and entropy enhancement capabilities. 1,[6][7][8][10][11][12]15,16 In most cases, the design is achieved with "open-loop" solutions, in which the nominal design does not include effective methods to handle the chaotic system parametric perturbation, caused by technological process variability or physical drifts related to, eg, aging, temperature variation, or environmental coupling.…”

Chaotic cellular neural network‐based true random number generator

“…Field programmable gate array-based applications provide high-speed implementation and reconfigurable design process. In cryptographic applications, FPGAs occupy an important place [28][29][30][31][32][33][34][35]. The proposed design in the third scenario is run on Virtex II Pro XC2VP30 FPGA development board by using Verilog HDL as the source type.…”

Logic minimization and wide fan‐in issues in DPL‐based cryptocircuits against power analysis attacks

“…A huge effort has been made in recent years to design and analyze the security of lightweight cryptographic algorithm implementations incorporating countermeasures against SCAs. [10][11][12] Despite the enormous range of countermeasures that have been developed, it is clear that additional work is required to provide more secure, more power-efficient solutions. When designing lightweight cryptocircuits, security and performance should be successfully maximized at a reasonable cost.…”