Enabling Hybrid Bonding on Intel Process

Temporary Direct Bonding by Low Temperature Deposited SiO2 for Chiplet Applications

“…High-performance semiconductor devices are a necessary component of systems such as artificial intelligence, cloud networks (that is, data centers), and edge devices. The concept of chiplets has received a great deal of attention as a means of reducing production costs while improving yield, power efficiency and performance. − Compared with systems on a chip and so-called monolithic chip devices, chiplet integration can provide improved yields by selecting known-good die (KGD) and can also adopt dies fabricated using different technical nodes in the system. These factors can lead to cost reduction and reduce the time from research and development to the marketing stage.…”

“…Chiplet integration typically requires a reduction of the vertical interconnection pitch. − Although the flip-chip micro bump technique has commonly been employed during die-to-wafer (D2W) bonding, this technology cannot ensure the alignment tolerance required for a pitch of less than 2 μm during thermal compression. In the case of D2W interactions involving finer pitches, hybrid bonding, in which dielectric layers are bonded with Cu pads in the absence of adhesive, can be employed.…”

“…In the case of D2W interactions involving finer pitches, hybrid bonding, in which dielectric layers are bonded with Cu pads in the absence of adhesive, can be employed. In fact, this approach is currently used to fabricate devices such as CMOS image sensors along with NAND and high bandwidth memory units based on wafer-to-wafer (W2W) bonding. − Hybrid bonding is also expected to have applications in D2W integration, although D2W hybrid bonding involves technological challenges. Examples of such challenges include die-level cleaning, activation, die handling, and balancing high alignment accuracy with throughput.…”