Enabling process technologies for advanced logic devices beyond FinFET era

Abstract

This invited talk describes the enabling process technologies for advanced logic devices beyond FinFET era. Gate-all-around (GAA) improves electrostatics over FinFET and enables continuous gate length scaling. Complementary FET (CFET), which is a structure of stacked transistors, is a next candidate architecture for the continuous cell height scaling enablement. Interconnect pitch scaling will also play crucial role for it and go with RC reduction knobs such as Cu damascene extension, post Cu and airgap. For better area usage and performance enhancement, backside power delivery network (PDN) is an attractive option. For these enablement, continuous process and tool advancement is necessary not only on film, etch, lithography and wet, but also on wafer bonding and thinning technologies. We will also review our recent progress in EUV related solutions including self-aligned patterning.