Energy and area efficient imprecise compressors for approximate multiplication at nanoscale

Ahmadinejad, Mohammad; Moaiyeri, Mohammad Hossein; Sabetzadeh, Farnaz

doi:10.1016/j.aeue.2019.152859

Cited by 94 publications

(76 citation statements)

References 30 publications

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“…Finally, we compare the proposed multiplier with the stateof-the-art multipliers based on inexact compressors [28], [32], [35], [36]. As these multipliers are 8-bit designs or implemented in FinFET technology, we compare them only in terms of PDP reductions and NMED reported in [28], [32], [35], [36]. Table 6 shows the reported NMED and PDP reduction for LOBO12−-12/8 the state-of-the-art multipliers based on inexact compressors.…”

Section: Synthesis Resultsmentioning

confidence: 99%

“…Furthermore, the authors proposed an algorithm for the placement of XOR-free compressors into the partial product tree. Ahmadinejad et al [35] designed inexact compressors in FinFET technology. Similarly to existing approaches, authors altered truth tables for exact 4:2 and 5:2 compressors to create inexact compressors.…”

Section: B Approximate Non-logarithmic Multipliersmentioning

confidence: 99%

“…Sabetzadeh et al [36] adopted majority logic approximation to develop inexact compressors in Fin-FET technology. Compared to [35], the proposed compressor is designed with a smaller number of transistors and exhibits a lower error. The authors report that this compressor is superior to its previous counterparts in terms of delay, power consumption, power delay product (PDP) and area, and improves these parameters on average by 32%, 68%, 78%, and 66%, respectively.…”

Section: B Approximate Non-logarithmic Multipliersmentioning

confidence: 99%

See 2 more Smart Citations

On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding

Pilipović

Bulić

2020

IEEE Access

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This paper proposes an energy-efficient approximate multiplier which combines radix-4 Booth encoding and logarithmic product approximation. Additionally, a datapath pruning technique is proposed and studied to reduce the hardware complexity of the multiplier. Various experiments were conducted to evaluate the multiplier's error performance and efficiency in terms of energy and area utilization. The reported results are based on simulations using TSMC-180nm. Also, the applicability of the proposed multiplier is examined in image sharpening and convolutional neural networks. The applicability assessment shows that the proposed multiplier can replace an exact multiplier and deliver up to a 75% reduction in energy consumption and up to a 50% reduction in area utilization. Comparative analysis with the state-of-the-art multipliers indicates the potential of the proposed approach as a novel design strategy for approximate multipliers. When compared to the state-of-the-art approximate non-logarithmic multipliers, the proposed multiplier offers smaller energy consumption with the same level of applicability in image processing and classification applications. On the other hand, some state-of-the-art approximate logarithmic multipliers exhibit lower energy consumption than the proposed multiplier but deliver significant performance degradation for the selected application cases. INDEX TERMS Approximate computing, arithmetic circuit design, booth encoding, logarithmic multipliers, multipliers, power-efficient processing, truncated multipliers.

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Section: Synthesis Resultsmentioning

confidence: 99%

Section: B Approximate Non-logarithmic Multipliersmentioning

confidence: 99%

Section: B Approximate Non-logarithmic Multipliersmentioning

confidence: 99%

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On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding

Pilipović

Bulić

2020

IEEE Access

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“…In an imprecise multiplier, partial product reduction can be realized through approximate compressors. Utilizing low‐complexity and energy‐efficient compressors with an adequate level of accuracy can remarkably enhance the entire performance of the multipliers, especially in error‐resilient applications such as image processing 19‐22 …”

Section: Introductionmentioning

confidence: 99%

Ultraefficient imprecise multipliers based on innovative 4:2 approximate compressors

Jooq

Ahmadinejad

Moaiyeri

2020

Circuit Theory & Apps

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SummaryThis study proposes two ultraefficient imprecise multipliers based on innovative 4:2 approximate compressor designs. The first proposed multiplier employs an ultracompact 8‐transistor 4:2 compressor to reduce the transistor count and energy dissipation. To improve the accuracy of the first proposed imprecise multiplier, the second multiplier also benefits from a semiaccurate 24‐transistor 4:2 approximate compressor for the high‐order bits. The 7‐nm fin field‐effect transistor (FinFET) technology, as one of the leading commercial technologies, is utilized to simulate the proposed multipliers in the environment. The simulation results indicate that the proposed imprecise multipliers show significant improvements regarding transistor count, delay, power, and power‐delay product as compared to their state‐of‐the‐art imprecise and exact counterparts. Along with the superior hardware efficiency, the MATLAB simulations demonstrate that the proposed multipliers also provide reasonable levels of accuracy. Moreover, a figure of merit (FOM) considering hardware efficiency and output quality is considered in order to evaluate the multipliers comprehensively. The FOM simulation results indicate that the proposed imprecise multipliers make a significant trade‐off between hardware efficiency and quality for approximate‐computing applications dealing with image multiplication.

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“…Among the discovered nanomaterials, carbon nanotubes with extraordinary mobility, ultrahigh immunity to the short channel effects, superior mean free path, and extreme current delivery are a breakthrough, surpassing other nanomaterials as the gate channel material in fabrication of high‐performance nanotransistors 23 . Carbon nanotube field‐effect transistors (CNTFETs) have laid the groundwork in nanoscale digital circuits and systems 24‐26 . However, few works have focused on the analog and RF application of these transistors 27‐29 .…”

Section: Introductionmentioning

confidence: 99%

A low‐power delay stage ring VCO based on wrap‐gate CNTFET technology for X‐band satellite communication applications

Jooq

Bozorgmehr

Mirzakuchaki

2020

Circuit Theory & Apps

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SummaryOver the past few years, with lower power consumption, reasonable layout area, and the ease of integration with standard circuit design technologies compared to the other counterparts, delay stage ring voltage‐controlled oscillators (VCOs) have been in the limelight of microelectronics scientists. However, few efforts have focused on representing high‐performance delay stage ring VCOs in the deep nanometric regime. In this regard, by virtue of outstanding electrical properties of carbon nanotube wrap‐gate transistors, this work aims to propose a carbon nanotube field‐effect transistor (CNTFET)–based delay stage ring VCO. After performing rigorous simulations, the proposed ring VCO which has been designed by 10‐nm gate‐all‐around (GAA) CNTFET technology shows suitable electrical performance metrics. The simulation results demonstrate that the proposed GAA‐CNTFET‐based ring VCO consumes 85.176 μW at with a 6.12‐ to 10.42‐GHz frequency tuning range. At the worst‐case noise conditions, the proposed design presents ‐90.747 dBc/Hz phase noise at 1 MHz offset frequency. With occupying 1.414 μm2 physical area, the proposed VCO is appropriate for the ultracompact nanoscale radio frequency apparatus. Our simulation results accentuate that with further improvements and commercializing the fabrication techniques for CNTFET transistors, the proposed GAA‐CNTFET‐based VCO can be considered as a potential candidate for X‐band satellite communication applications.

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Energy and area efficient imprecise compressors for approximate multiplication at nanoscale

Cited by 94 publications

References 30 publications

On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding

On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding

Ultraefficient imprecise multipliers based on innovative 4:2 approximate compressors

A low‐power delay stage ring VCO based on wrap‐gate CNTFET technology for X‐band satellite communication applications

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