Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology

Nikoubin, Tooraj; Grailoo, Mahdieh; Li, Changzhi

doi:10.1109/tvlsi.2015.2393717

Cited by 23 publications

(8 citation statements)

References 19 publications

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“…CDM has the potential to be used for both of these methods. SCDM is the design methodology which can systematically generate elementary basic cells (EBC) using a binary decision diagram (BDD), and wisely choose circuit components based on specific targets [18], [19]. This takes place when mentioned features are not considered in the regular CDM.…”

Section: B Cdm Methodologymentioning

confidence: 99%

Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells

Nikoubin

basireddy

2019

IEEE Access

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Transistor network optimization is an effective way of improving the VLSI circuit design. Recent papers demonstrate the graph-based or library-based methodologies of the supergate (SG) design. This design approach is the direct design of the functions at the transistor level that can provide circuits with fewer transistors when compared with the conventional methods. In addition to the transistor count, the symmetry structure of the circuit, the number of transistors on the critical path, and multi-outputs and multifunctional cells are considered in this paper, as the three crucial parameters for the efficient SG cell design. Thus, the cell design methodology (CDM) logic style is used as a new approach for the SG design with some changes in the design flow for improving circuit characteristics. The proposed CDM-SG design methodology can produce a single output, complementary output, and multi-functional output SG cells. The comparison of the proposed CDM-SG cells with conventional SG cells shows a significant improvement on the layout area, power and energy consumption, and speed. The proposed CDM-SG cells with spiral structure are multioutput and multi-functional cells, which can significantly improve the circuit characteristics by improving the number of output functions over the cell area. INDEX TERMS Supergate design methodology, cell design methodology, energy-power-area efficient, SP&NSP transistor network, graph-based CDM.

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Section: B Cdm Methodologymentioning

confidence: 99%

Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells

Nikoubin

basireddy

2019

IEEE Access

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“…The static and transient performance depends upon the availability of high-quality switches with low parasitic resistance and capacitance [10]- [11]. Its static power dissipation is constant and dynamic power is very less.…”

Section: Transmission Gate Logicmentioning

confidence: 99%

Efficient Layout Design using Transmission Gate in 45nm Technology

Nishant¹,

Meenakshi²,

Mehra³

2019

IJETR

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XNOR-XOR gates are generally used in arithmetic and logic circuits. This paper presents the performance comparison analysis for the combination of XNOR-XOR circuit by using transmission gate. The transmission gate has consumed only 10 transistors as compared to 16 transistors in case of conventional design. The performance of the simulated circuit has been evaluated and compared in terms of propagation delay, power & area consumption using 45nm technology. It can be observed from the simulated results that proposed circuit consume 63.97% less area and 90.66% less power as compared to existing design. The speed performance of proposed design is also improved by 85.38% to provide high performance solution for VLSI applications.

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“…Tooraj Nikoubin [3] proposed three inputs xor/xnor circuit using a systematic cell design methodology (SCDM) in hybrid CMOS logic style. Their design shows, full swing and balanced outputs; even with supply voltage scaling they perform well and in the critical path they contain two transistors.…”

Section: Literature Surveymentioning

confidence: 99%

“…Now it is recognized that they also enable a very useful mode of MOSFET operation, and that the sub threshold region of operation is as important as the traditional cut-off, linear, and saturations regions of operation. [3]- [5].…”

Section: Proposed Architecturementioning

confidence: 99%