Energy Efficiency Exploration on the ZYNQ Ultrascale+

Giorgi, Roberto; Khalili, Farnam; Procaccini, Marco

doi:10.1109/icm.2018.8704092

Cited by 4 publications

(2 citation statements)

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“…Simulator. Based on our experience of the AXIOM project [4, 12,13], the main motivation behind the choice of the COTSon simulation framework resides in the "functional-directed" approach [16]. COTSon also permits to model a complete system like a Table 2: Interesting features of simulators for high-performance computing architectures.…”

Section: Dse Toolset and Cotsonmentioning

confidence: 99%

“…ere are parameters which make simulators preferable to reach a certain level of performance, scalability, and accuracy as well as reproducibility and observability. Based on the experience of previous projects such as TERAFLUX [6,7], ERA [8,9], AXIOM [4, [10][11][12][13], and SARC [14,15], we choose to rely on the HP-Labs COTSon simulation infrastructure [16]. e key feature of COTSon that is useful in HLS design is its "functional-directed" approach, which separates the functional simulation from the timing one.…”

Section: Introductionmentioning

confidence: 99%

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Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

Giorgi

Khalili

Procaccini

2019

International Journal of Reconfigurable Computing

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Translating a system requirement into a low-level representation (e.g., register transfer level or RTL) is the typical goal of the design of FPGA-based systems. However, the Design Space Exploration (DSE) needed to identify the final architecture may be time consuming, even when using high-level synthesis (HLS) tools. In this article, we illustrate our hybrid methodology, which uses a frontend for HLS so that the DSE is performed more rapidly by using a higher level abstraction, but without losing accuracy, thanks to the HP-Labs COTSon simulation infrastructure in combination with our DSE tools (MYDSE tools). In particular, this proposed methodology proved useful to achieve an appropriate design of a whole system in a shorter time than trying to design everything directly in HLS. Our motivating problem was to deploy a novel execution model called data-flow threads (DF-Threads) running on yet-to-be-designed hardware. For that goal, directly using the HLS was too premature in the design cycle. Therefore, a key point of our methodology consists in defining the first prototype in our simulation framework and gradually migrating the design into the Xilinx HLS after validating the key performance metrics of our novel system in the simulator. To explain this workflow, we first use a simple driving example consisting in the modelling of a two-way associative cache. Then, we explain how we generalized this methodology and describe the types of results that we were able to analyze in the AXIOM project, which helped us reduce the development time from months/weeks to days/hours.

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Section: Dse Toolset and Cotsonmentioning

confidence: 99%