Energy-Efficient and PVT-Tolerant CNFET-Based Ternary Full Adder Cell

Tabrizchi, Sepehr; Sharifi, Fazel; Dehghani, Parisa

doi:10.1007/s00034-020-01638-w

Cited by 10 publications

(3 citation statements)

References 33 publications

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“…The other two papers have been published by IEEE ELECTRON DEVICE LETT [33] and IEEE OJ-NANO [34]. Furthermore, CSSP (Springer) [35][36][37][38][39][40][41][42] and MICROELECTR J (Elsevier) [43][44][45][46][47][48][49][50] with eight papers each, and INT J ELECTRON (Taylor & Francis) [51][52][53][54][55] and IET CIRC DEVICE SYST (IET/IEE) [56][57][58][59][60] with five papers each are the journals with the highest number of publications relevant to the subject of THAs and TFAs in other publishers. IEEE ISMVL, with 11 papers [61][62][63][64][65][66][67][68][69][70][71], is the one that stands out among conferences.…”

Section: Research Methods and Bibliographic Informationmentioning

confidence: 99%

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Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Nemati

Kashani

Mirzaee

2023

IET Circuits, Devices & Syst

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The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or V DD . This way, in a single-V DD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count. K E Y W O R D Sadders, carbon nanotube field effect transistors, digital arithmetic, multivalued logic, multivalued logic circuits, ternary logicThis is an open access article under the terms of the Creative Commons Attribution-NonCommercial License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited and is not used for commercial purposes.

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Section: Research Methods and Bibliographic Informationmentioning

confidence: 99%

“…We have found 125 related papers [11–135], 20% of which have been published in IEEE journals. To be more specific, there are 15 IEEE Transactions [11–25], five IEEE Access [26–30], and two JSSC papers [31, 32].…”

Section: Literature Review and Backgroundmentioning

confidence: 99%

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Nemati

Kashani

Mirzaee

2023

IET Circuits, Devices & Syst

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“…14 Single-walled Carbon Nanotubes can be divided into three categories based on the arrangement of carbon atoms in the cross section of the tube: Armchair and Chiral, which have metal properties, and Zigzag, which has semiconductor properties. 15 A Single-Walled Carbon Nanotube (SWNT) can be observed as a graphite sheet (carbon hexagonal lattice) piped as a cylinder, typically has several nanometers in diameter and several micrometers in length. Depending on the direction of rotation and tubing (their geometric configuration), SWNTs can have different electronic properties.…”

Section: Overview Of Cnfet Technologymentioning

confidence: 99%

A New Quaternary Full Adder Cell based on CNFET for Use in Fast Arithmetic Circuits

Bolourforoush¹,

Ghanatghestani²

2022

ECS J. Solid State Sci. Technol.

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Multi-valued logic potentially increases the efficiency of arithmetic circuits and digital ‎signal processing. Quaternary logic can be suggested as a solution to the problem of power ‎consumption and connection complexity in binary digital systems. The possibility of having ‎several threshold voltage levels using the carbon nanotube field-effect transistor ‎results in the widespread use of this technology in the design of multi-valued circuits. Here, a quaternary full adder cell is proposed. The main goal of the proposed circuit ‎is to reduce the critical delay path in the quaternary full adder circuit using a parallel ‎design. The proposed circuit is compared with four quaternary full adders based on ‎simulation results using HSPICE in 32 nm technology. The experimental results show the ‎higher performance of the proposed quaternary full adder cell than the state-of-the-art ‎designs.‎

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