Energy-Efficient CNTFET-RRAM Based Ternary Logic Design

Haq, Shams Ul; Sharma, Vijay Kumar

doi:10.1109/aece59614.2023.10428386

Cited by 3 publications

(1 citation statement)

References 19 publications

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“…The V th adjustment of CNTFETs by chirality modulation has proven to be prolific in terms of energy efficiency and speed [4][5][6]. The carbon nanotubes (CNT) offer some astonishing advantages which include high I ON /I OFF [7], absence of mobility degradation [8], and ballistic transport [9,10]. Other exceptional benefits include less sensitivity to process variations [11], ultra-thin body [12,13] and variation of bandgap within a single material [14].…”

Section: Introductionmentioning

confidence: 99%

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

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In this paper, a carbon nanotube field-effect transistor (CNTFET) based low power and robust ternary SRAM (TSRAM) cell with enhanced static noise margin (SNM) has been proposed. The proposed cell uses a low-power cell core and a stack of 2 CNTFETs to discharge the read bit line (RBL) to ground, unlike the previous SRAM designs which use read buffers or transmission gates (TG) to alter the voltage levels on the RBL. The proposed TSRAM cell has been simulated relentlessly, using the Stanford 32 nm CNTFET technology mode file with Synopsis HSPICE tool under various operating conditions. Unlike other designs, the cross-coupled ternary inverters used as the cell core in the proposed TSRAM show higher gain and steep curves in the transition region mitigating the static power of the cell. The simulation results exhibit improvements in performance parameters like power consumption, energy, noise margins, and reliability. At 0.9 V supply voltage, the proposed TSRAM cell offers 52.44% and 43.17% reduction in write and read static power, a PDP reduction of 35.29% in comparison, and a 36.36% improvement in SNM compared to best designs under investigation. Also, the proposed TSRAM design shows higher robustness compared to other designs.

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Section: Introductionmentioning

confidence: 99%

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

Self Cite

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Tri-state GNRFET-based fast and energy-efficient ternary multiplier

Ul Haq,

Abbasian,

Khurshid

et al. 2024

AEU - International Journal of Electronics and Communications

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An efficient design methodology for a tri-state multiplier circuit in carbon nanotube technology

Haq,

Orouji,

Khurshid

et al. 2024

Phys. Scr.

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This study delves into the computational aspects of ternary logic and the use of carbon nanotube field-effect transistors (CNTFETs) to develop an energy-efficient and robust ternary multiplier (TMUL). Leveraging the exceptional qualities of CNTFETs, such as balanced electron and hole mobility and easy modulation of threshold voltage, the research aims to achieve the desired designs. An innovative design method is employed, recommending a reduced count of logic gates for achieving necessary logic levels. These gates are then utilized to manage the activation and deactivation of the primary transistors within the TMUL cell to convey the intended logics to the outputs. Moreover, the suggested design is focused on a single-V DD , enhancing compatibility with the goals of a multi-valued logic platform. The proposed circuit is validated using Synopsis HSPICE simulator and Stanford’s standard 32-nm CNTFET model file. Comparative analysis with existing TMUL designs demonstrates a 25.43% decrease in average power consumption, a 42.24% reduction in power-delay product (PDP), and a 24.69% decrease in energy-delay product (EDP). The design undergoes thorough simulations under various conditions including load variations and process, voltage, and temperature (PVT) fluctuations to confirm its reliability and robustness.

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Energy-Efficient CNTFET-RRAM Based Ternary Logic Design

Cited by 3 publications

References 19 publications

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Tri-state GNRFET-based fast and energy-efficient ternary multiplier

An efficient design methodology for a tri-state multiplier circuit in carbon nanotube technology

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