Energy estimation in SystemC with Powersim

Orcioni, Simone; Giammarini, Marco; Scavongelli, Cristiano; Vece, Giovanni B.; Conti, Massimo

doi:10.1016/j.vlsi.2016.04.006

Cited by 8 publications

(6 citation statements)

References 16 publications

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“…In the recent research works, design verification against the power aspect is performed at different abstraction levels with a trade-off between speed and accuracy. Some works such as [46], [47], [61], [62] perform power analysis at system level targeting high simulation speed and low power optimization flexibility similar to the accuracy achievable at lower levels. In [46], the authors applied their approach to SRAM and AES encryption IPs and obtained a significant simulation speed-up in comparison to gate-level simulation with a high fidelity of the system-level power simulation.…”

Section: Power Consumptionmentioning

confidence: 99%

“…In [46], the authors applied their approach to SRAM and AES encryption IPs and obtained a significant simulation speed-up in comparison to gate-level simulation with a high fidelity of the system-level power simulation. A promising software tool for power simulation in SystemC designs is the Powersim framework [47], [62]. In [47], a methodology to estimate the dissipation of energy in hardware at any level of abstraction is proposed.…”

Section: Power Consumptionmentioning

confidence: 99%

“…A promising software tool for power simulation in SystemC designs is the Powersim framework [47], [62]. In [47], a methodology to estimate the dissipation of energy in hardware at any level of abstraction is proposed. In [62], the authors propose a SystemC class library aimed at calculation of energy consumption of hardware described at system level.…”

Section: Power Consumptionmentioning

confidence: 99%

See 2 more Smart Citations

Towards Multidimensional Verification: Where Functional Meets Non-Functional

Jenihhin

Lai

Ghasempouri

et al. 2018

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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Trends in advanced electronic systems' design have a notable impact on design verification technologies. The recent paradigms of Internet-of-Things (IoT) and Cyber-Physical Systems (CPS) assume devices immersed in physical environments, significantly constrained in resources and expected to provide levels of security, privacy, reliability, performance and low power features. In recent years, numerous extra-functional aspects of electronic systems were brought to the front and imply verification of hardware design models in multidimensional space along with the functional concerns of the target system. However, different from the software domain such a holistic approach remains underdeveloped. The contributions of this paper are a taxonomy for multidimensional hardware verification aspects, a state-of-the-art survey of related research works and trends towards the multidimensional verification concept. The concept is motivated by an example for the functional and power verification dimensions.

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Section: Power Consumptionmentioning

confidence: 99%

Section: Power Consumptionmentioning

confidence: 99%

Section: Power Consumptionmentioning

confidence: 99%

See 1 more Smart Citation

Towards Multidimensional Verification: Where Functional Meets Non-Functional

Jenihhin

Lai

Ghasempouri

et al. 2018

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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show abstract

“…We paid particular attention to the DCT module design, trying to find a compromise between performances and resource utilization. The SystemC model of the proposed architecture with a deep system level power analysis is reported in [23][24][25].…”

Section: The Proposed Architecturementioning

confidence: 99%

FPGA implementation of JPEG encoder architectures for wireless networks

Scavongelli

Conti

2016

J Embedded Systems

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Due to its relative simplicity, the JPEG compression algorithm requires less hardware or software resources with respect to new compression algorithms, for example the JPEG2000 and the JPEG XR. This makes it suitable for low-power applications. Moreover, features embedded in the JPEG2000 and the JPEG XR, such as the scalability of the image stream, can be added to the main JPEG core, making an encoder useful for example in a video surveillance wireless network. Nevertheless, actual JPEG dedicated hardware realizations do not implement many features of the compression standard. In this work, we developed several JPEG encoder architectures with full real-time reconfigurability and support for the restart intervals and, for a simple scalability mechanism, the scan scheme. These features make the architectures suitable for the use in low-bandwidth, low-power wireless networks. The JPEG encoder architectures have been developed starting from a SystemC model and then implemented in a FPGA.

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“…Another interesting contribution is the Powersim C++ class library presented in [33]. It monitors the C++ operators during the simulation of a high-level of abstraction model developed using SystemC in order to estimate a given hardware’s power consumption when provided with an energy model.…”

Section: Introductionmentioning

confidence: 99%

A System-Level Methodology for the Design of Reliable Low-Power Wireless Sensor Networks

Brini

Deslandes

Nabki

2019

Sensors

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Innovative Internet of Things (IoT) applications with strict performance and energy consumption requirements and where the agile collection of data is paramount are arising. Wireless sensor networks (WSNs) represent a promising solution as they can be easily deployed to sense, process, and forward data. The large number of Sensor Nodes (SNs) composing a WSN are expected to be autonomous, with a node’s lifetime dictated by the battery’s size. As the form factor of the SN is critical in various use cases, minimizing energy consumption while ensuring availability becomes a priority. Moreover, energy harvesting techniques are increasingly considered as a viable solution for building an entirely green SN and prolonging its lifetime. In the process of building a SN and in the absence of a clear and well-rounded methodology, the designer can easily make unfounded and suboptimal decisions about the right hardware components, their configuration, and reliable data communication techniques, such as automatic repeat request (ARQ) and forward error correction (FEC). In this paper, a methodology to design, configure, and deploy a reliable ultra-low power WSNs is proposed. A comprehensive energy model and a realistic path-loss (PL) model of the sensor node are also established. Through estimations and field measurements it is proven that, following the proposed methodology, the designer can thoroughly explore the design space and the make most favorable decisions when choosing commercial off-the-shelf (COTS) components, configuring the node, and deploying a reliable and energy-efficient WSN.

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Energy estimation in SystemC with Powersim

Cited by 8 publications

References 16 publications

Towards Multidimensional Verification: Where Functional Meets Non-Functional

Towards Multidimensional Verification: Where Functional Meets Non-Functional

FPGA implementation of JPEG encoder architectures for wireless networks

A System-Level Methodology for the Design of Reliable Low-Power Wireless Sensor Networks

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