Energy management for real-time embedded applications with compiler support

AbouGhazaleh, Nevine; Childers, Bruce R.; Mossé, Daniel; Melhem, Rami; Craven, Matthew

doi:10.1145/780768.780771

Cited by 6 publications

(7 citation statements)

References 1 publication

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“…One solution is to use both the compiler and the operating system to adapt performance and reduce energy consumption of the processor. The collaborative IntraDVS [1] uses such an approach and provides a systematic methodology to partition a program into segments considering branch, loop and procedure call.…”

Section: Segment-based Intradvsmentioning

confidence: 99%

Power-Aware Resource Management Techniques for Low-Power Embedded Systems

Kim¹,

Rosing²

2007

Chapman &Amp; Hall/CRC Computer &Amp; Information Science Series

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For example, consider a task with a deadline of 25 msec, running on a processor with the 50 MHz clock speed and 5.0 V supply voltage. If the task requires 5 • 10 5 cycles for its execution, the processor executes the task in 10 msec and becomes idle for the remaining 15 msec. (We call this type of an idle interval the slack time.) However, if the clock speed and the supply voltage are lowered to 20 MHz and 2.0 V, it finishes the task at its deadline (= 25 msec), resulting in 84% energy reduction. Since lowering the supply voltage also decreases the maximum achievable clock speed [43], various DVS algorithms for real-time systems have the goal of reducing supply voltage dynamically to the lowest possible level while satisfying the tasks' timing constraints. For real-time systems where timing constraints must be strictly satisfied, a fundamental energy-delay tradeoff makes it more challenging to dynamically adjust the supply voltage so that the energy consumption is minimized while not violating the timing requirements. In this chapter, we focus on DVS algorithms for hard real-time systems. On the other hand, dynamic power management decreases the energy consumption by selectively placing idle components into lower power states. At the minimum, the device needs to stay in the low-power state for long enough (defined as the break even time) to recuperate the cost of transitioning in and out of the state. The break even time T BE , as defined in Equation 1.1, is a function of the power consumption in the active state, P on , the amount of power consumed in the low power state, P sleep , and the cost of transition in terms of both time, T tr , and power, P pr. If it was possible to predict ahead of time the exact length of each idle period, then the ideal power management policy would place a device in the sleep state only when idle period will be longer than the break even time. Unfortunately, in most real systems such perfect prediction of idle period is not possible. As a result, one of the primary tasks DPM algorithms have is to predict when the idle period will be long enough to amortize the cost of transition to a low power state, and to select the state to transition to. Three classes of policies can be defined-timeout based, predictive and stochastic. The policies in each class differ in the way prediction of the length of the idle period is made, and the timing of the actual transition into the low power state (e.g., transitioning immediately at the start of an idle period vs. after some amount of idle time has passed).

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Section: Segment-based Intradvsmentioning

confidence: 99%

Power-Aware Resource Management Techniques for Low-Power Embedded Systems

Kim¹,

Rosing²

2007

Chapman &Amp; Hall/CRC Computer &Amp; Information Science Series

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“…Branching edges in control-flow graph (CFG) that drop the remaining worst-case execution time faster than the current execution rates are selected as voltage/frequency scaling points. In AbouGhazaleh et al [2003], a power-management point routine is invoked periodically to adjust the processor voltage/frequency based on the worst-case remaining cycles, which are collected at run-time by instrumenting code at compile time. Thus, there exists run-time overhead related to the mode decision in addition to the switching overhead.…”

Section: Related Workmentioning

confidence: 99%

Intraprogram dynamic voltage scaling

Xie

Martonosi

Malik

2004

ACM Trans. Archit. Code Optim.

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Dynamic voltage scaling (DVS) has become an important dynamic power-management technique to save energy. DVS tunes the power-performance tradeoff to the needs of the application. The goal is to minimize energy consumption while meeting performance needs. Since CPU power consumption is strongly dependent on the supply voltage, DVS exploits the ability to control the power consumption by varying a processor's supply voltage and clock frequency. However, because of the energy and time overhead associated with switching DVS modes, DVS control has been used mainly at the interprogram level. In this paper, we explore the opportunities and limits of intraprogram DVS scheduling. An analytical model is derived to predict the maximum energy savings that can be obtained using intraprogram DVS given a few known program and processor parameters. This model gives insights into scenarios where energy consumption benefits from intraprogram DVS and those where there is no benefit. The model helps us extrapolate the benefits of intraprogram DVS into the future as processor parameters change. We then examine how much of these predicted benefits can actually be achieved through compile-time optimal settings of DVS modes. We extend an existing mixed-integer linear program formulation for this scheduling problem by accurately accounting for DVS energy switching overhead, by providing finer-grained control on settings and by considering multiple data categories in the optimization. Overall, this research provides a comprehensive view of intraprogram compile-time DVS management, providing both practical techniques for its immediate deployment as well theoretical bounds for use into the future.

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“…In the PMH-placement algorithm [AbouGhazaleh et al 2003a], while traversing the CFG of a procedure, a cycle counter ac is incremented by the value of the elapsed worst-case cycles of each traversed region. A PMH is inserted in the code just before this counter exceeds the PMP interval and the counter is reset.…”

Section: Offline Placementmentioning

confidence: 99%

Collaborative operating system and compiler power management for real-time applications

AbouGhazaleh

Mossé

Childers

et al.

The 9th IEEE Real-Time and Embedded Technology and Applications Symposium, 2003. Proceedings.

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Managing energy consumption has become vitally important to battery-operated portable and embedded systems. Dynamic voltage scaling (DVS) reduces the processor's dynamic power consumption quadratically at the expense of linearly decreasing the performance. When reducing energy with DVS for real-time systems, one must consider the performance penalty to ensure that deadlines can be met. In this paper, we introduce a novel collaborative approach between the compiler and the operating system (OS) to reduce energy consumption. We use the compiler to annotate an application's source code with path-dependent information called power-management hints (PMHs). This fine-grained information captures the temporal behavior of the application, which varies by executing different paths. During program execution, the OS periodically changes the processor's frequency and voltage based on the temporal information provided by the PMHs. These speed adaptation points are called power-management points (PMPs). We evaluate our scheme using three embedded applications: a video decoder, automatic target recognition, and a sub-band tuner. Our scheme shows an energy reduction of up to 57% over no power-management and up to 32% over a static power-management scheme. We compare our scheme to other schemes that solely utilize PMPs for power-management and show experimentally that our scheme achieves more energy savings. We also analyze the advantages and disadvantages of our approach relative to another compiler-directed scheme.

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Energy management for real-time embedded applications with compiler support

Cited by 6 publications

References 1 publication

Power-Aware Resource Management Techniques for Low-Power Embedded Systems

Power-Aware Resource Management Techniques for Low-Power Embedded Systems

Intraprogram dynamic voltage scaling

Collaborative operating system and compiler power management for real-time applications

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