2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2006
DOI: 10.1109/dft.2006.27
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Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method

Abstract: In this paper, we apply a technique to improve diagnosis resolution for delay faults. The method analyze the structure of test paths to find the bottleneck of the diagnosis process. Then we use the information to search for additional paths (by extending from the current paths) in order to effectively cut down the number of faulty candidates. The experimental result shows that the proposed technique can reduce the efforts of diagnosis by a meaningful amount. In ISCAS'89 benchmarks, the method can improve the a… Show more

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