Enzian: an open, general, CPU/FPGA platform for systems software research

Cock, David; Ramdas, Abishek; Schwyn, Daniel; Giardino, Michael; Turowski, Adam; He, Zhenhao; Hossle, Nora; Korolija, Dario; Licciardello, Melissa; Martsenko, Kristina; Achermann, Reto; Alonso, Gustavo; Roscoe, Timothy

doi:10.1145/3503222.3507742

Cited by 27 publications

(9 citation statements)

References 40 publications

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“…This makes cc-accelerators suitable for µs-scale acceleration/offloading. Currently, some cc-accelerators are commercially available [27,28,68] and more commercial cc-accelerators will emerge as the next-generation Intel Xeon CPUs begins to support CXL [127].…”

Section: Cache-coherent Interconnects and Acceleratorsmentioning

confidence: 99%

“…The local cache is also in the coherence domain and handled by the coherence controller. The ORCA cc-accelerator may have its own local memory controller and memory [28,30] that constitutes the unified memory space with the CPU memory. In such an architecture, the CPU may allocate application data to the cc-accelerator's local memory, as the NUMA-aware memory management does in the modern Linux kernel.…”

Section: Orca Cc-accelerator Architecturementioning

confidence: 99%

“…Besides, the cpoll region must be pinned in the cc-accelerator's local cache. We expect that such limitations will be effortlessly tackled when ORCA is implemented in CXL-based devices [30] or Enzian [28].…”

Section: Orca Implementation and Evaluation Setupmentioning

confidence: 99%

“…Since the in-package FPGA is not extendable, to explore the potential of ORCA's performance on future platforms, we also use a stand-alone Xilinx U280 FPGA card [169] with 32 GB DDR4 memory and 8 GB HBM2 to emulate a cc-accelerator with local coherent memory [28,30]. Prior work [162] has shown that these two types of memory can achieve ∼36 GB/s and ∼425 GB/s throughput, respectively.…”

Section: Orca Implementation and Evaluation Setupmentioning

confidence: 99%

“…Tackling the limitations of the current solutions, this paper proposes ORCA (Offloading with RDMA and Cc-Accelerator), a holistic modularized solution to cost-effectively and efficiently serve µs-scale datacenter applications. Specifically, ORCA proposes a server with a standard RDMA NIC (RNIC) and a cache-coherent accelerator (ccaccelerator) [28,68] connected to an emerging cache-coherent off-chip interconnect (cc-interconnect) such as CXL [31]. The RNIC, cc-accelerator, and the server CPU work synergistically in a fine-grained fashion, to efficiently offload network and application processing from the server CPU.…”

Section: Introductionmentioning

confidence: 99%

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ORCA: A Network and Architecture Co-design for Offloading us-scale Datacenter Applications

Yang¹,

Huang²,

Sun³

et al. 2022

Preprint

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Responding to the "datacenter tax" and "killer microseconds" problems for datacenter applications, diverse solutions including Smart NIC-based ones have been proposed. Nonetheless, they often suffer from high overhead of communications over network and/or PCIe links. To tackle the limitations of the current solutions, this paper proposes ORCA, a holistic network and architecture co-design solution that leverages current RDMA and emerging cache-coherent off-chip interconnect technologies. Specifically, ORCA consists of four hardware and software components: (1) unified abstraction of inter-and intra-machine communications managed by one-sided RDMA write and cache-coherent memory write; (2) efficient notification of requests to accelerators assisted by cache coherence; (3) cache-coherent accelerator architecture directly processing requests received by NIC; and (4) adaptive device-tohost data transfer for modern server memory systems consisting of both DRAM and NVM exploiting state-of-the-art features in CPUs and PCIe. We prototype ORCA with a commercial system and evaluate three popular datacenter applications: in-memory key-value store, chain replication-based distributed transaction system, and deep learning recommendation model inference. The evaluation shows that ORCA provides 30.1∼69.1% lower latency, up to 2.5× higher throughput, and ∼ 3× higher power efficiency than the current state-of-the-art solutions.

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Section: Cache-coherent Interconnects and Acceleratorsmentioning

confidence: 99%

Section: Orca Cc-accelerator Architecturementioning

confidence: 99%

Section: Orca Implementation and Evaluation Setupmentioning

confidence: 99%

Section: Orca Implementation and Evaluation Setupmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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