EPIC: Ending Piracy of Integrated Circuits

Abstract

As semiconductor manufacturing requires greater capital investments, the use of contract foundries has grown dramatically, increasing exposure to mask theft and unauthorized excess production. While only recently studied, IC piracy has now become a major challenge for the electronics and defense industries [6].We propose a novel comprehensive technique to end piracy of integrated circuits (EPIC). It requires that every chip be activated with an external key, which can only be generated by the holder of IP rights, and cannot be duplicated. EPIC is based on (i) automatically-generated chip IDs, (ii) a novel combinational locking algorithm, and (iii) innovative use of public-key cryptography. Our evaluation suggests that the overhead of EPIC on circuit delay and power is negligible, and the standard flows for verification

Reverse engineering circuits using behavioral pattern mining

“…Our technique addresses the REHLD problem for a system integrator who has not designed the circuit being reverse-engineered, but instead needs to verify its functionality prior to integration. We do not address the problem of untrusted manufacturing and IC piracy, where the designer is trusted, which can be tackled by techniques such as EPIC [19]. Our technique is complementary to other recent work on malicious trojan circuit detection (e.g., [12,21]).…”

Logic Locking Using Hybrid CMOS and Emerging SiNW FETs

“…For instance, by adding few XOR/XNOR key-gates (less than 5% of the total number of gates in an original circuit), the penalty of the power and area is approximately larger than 31% and 20% for the majority benchmark circuits, respectively [20]. It is worth mentioning that this amount of adding ratio is not enough to prevent the brute force attack, where the key-size should at least be larger than 64 bits [19]. With the scaling of CMOS technology, it becomes more expensive to achieve similar security level by compromising the performance.…”

“…In combinational logic locking, XOR/XNOR key gates are introduced to mask the correct functionality of IP design [18][19][20]. Roy et al [19] proposed a chip-locking system for active IC metering, while targeted to make physical tampering infeasible. The chip-locking framework inserts XOR/XNOR key gates with fan-ins connected to the bits of keys that activate the circuit.…”

E2LEMI:Energy-Efficient Logic Encryption Using Multiplexer Insertion

“…In [19][20][21], the authors presented a technique to insert XOR/XNOR gates randomly into an original circuit to conceal its functionality. Upon inserting the valid key, the end-user can get the correct output.…”