Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters

Coşkun, Kemal Çağlar; Hassan, Muhammad; Drechsler, Rolf

doi:10.1109/ddecs54261.2022.9770142

Cited by 2 publications

(4 citation statements)

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“…We leverage Signal-Flow Graphs (SFG) as an intermediate representation between the SPICElevel and the system-level model, which the canonical representation also relies on. In particular, the developed method extends the applicability of the method in [19] to the class of complex single-input single-output (SISO) linear analog circuits with passive and active components. Many analog circuits fall into the linear category, such as various classic electronic circuits and many analog filters.…”

Section: Contributionmentioning

confidence: 99%

“…Some examples of supported circuits are analog High-Pass Filters (HPF), averager circuits, amplifiers operated in their linear region, linear computation circuits, etc., and their combinations. Additionally, the method is extended to handle more complex behavioral models with respect to the simple LTF models used in [19]. We demonstrate the applicability of the developed methodology by successfully applying it to complex linear analog circuits.…”

Section: Contributionmentioning

confidence: 99%

“…In this article, we significantly extend the methods and applicability of our novel equivalence checking methodology from [19], which is, to the best of our knowledge, the first of its kind. Essentially, our approach operates directly on the systemlevel and SPICE-level models by combining the linear graph modeling technique with several graph operations to transform these complex models into a canonical representation.…”

Section: Contributionmentioning

confidence: 99%

“…Therefore, even if these methods claim equivalence, the models might still behave differently in an overlooked gap. Our proposed equivalence checking methodology, which we introduced in [19], does not have this issue as the analysis and modification methods used, such as linear graph modeling and graph reduction, statically analyze the structure of the models. On the other hand, the applicability of the method was limited to linear analog filter circuits.…”

Section: Related Workmentioning

confidence: 99%

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Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits

Coşkun

Hassan

Drechsler

2022

Chips

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Due to the increasing complexity of analog circuits and their integration into System-on-Chips (SoC), the analog design and verification industry would greatly benefit from an expansion of system-level methodologies using SystemC AMS. These can provide a speed increase of over 100,000× in comparison to SPICE-level simulations and allow interoperability with digital tools at the system-level. However, a key barrier to the expansion of system-level tools for analog circuits is the lack of confidence in system-level models implemented in SystemC AMS. Functional equivalence of single Laplace Transfer Function (LTF) system-level models to respective SPICE-level models was successfully demonstrated recently. However, this is clearly not sufficient, as the complex systems comprise multiple LTF modules. In this article, we go beyond single LTF models, i.e., we develop a novel graph-based methodology to formally check equivalence between complex system-level and SPICE-level representations of Single-Input Single-Output (SISO) linear analog circuits, such as High-Pass Filters (HPF). To achieve this, first, we introduce a canonical representation in the form of a Signal-Flow Graph (SFG), which is used to functionally map the two representations from separate modeling levels. This canonical representation consists of the input and output nodes and a single edge between them with an LTF as its weight. Second, we create an SFG representation with linear graph modeling for SPICE-level models, whereas for system-level models we extract an SFG from the behavioral description. We then transform the SFG representations into the canonical representation by utilizing three graph manipulation techniques, namely node removal, parallel edge unification, and reflexive edge elimination. This allows us to establish functional equivalence between complex system-level models and SPICE-level models. We demonstrate the applicability of the proposed methodology by successfully applying it to complex circuits.

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Section: Contributionmentioning

confidence: 99%

Section: Contributionmentioning

confidence: 99%

Section: Contributionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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