Er and Pt Gate Electrodes Formed on SiO[sub 2] Gate Dielectrics

Abstract

We investigated the electrical and structural properties of W/Er/SiO 2 and Pt/SiO 2 gate stacks. W/Er/SiO 2 gate stacks exhibited increased capacitance after rapid thermal annealing ͑RTA͒ process while the capacitance of Pt/SiO 2 gate stacks remained unchangeable regardless of RTA process. Because of the physical plasma damage that occurred during the sputtering deposition process, Pt penetration led to a decrease in the SiO 2 film thickness of Pt/SiO 2 gate stacks. This resulted in the reduction of the equivalent oxide thickness compared to the poly-Si/SiO 2 gate stack. A relatively small flatband voltage shift of W/Er/SiO 2 gate stacks was attributed to the reduction of effective oxide charge caused by interfacial reaction between Er and SiO 2 films.With continuous scaling down of complementary metal oxide semiconductor ͑CMOS͒ to the 45 nm technology node and beyond, a metal gate is expected to replace a conventional polycrystalline silicon ͑poly-Si͒ electrode for realizing a high device performance. The metal gate has superior advantages over the poly-Si gate, such as very low gate resistance, no dopant penetration to channel, and good process compatibility with high-k gate dielectric. 1-4 In addition, it does not suffer from increasing effective oxide thickness ͑EOT͒ caused by poly-depletion effect. 5 Generally, the sputtering deposition method has been widely used for forming metal gate electrodes due to its low cost of operation, low process temperature, and precise controllability of various metal thin layers. However, during sputtering deposition process, the gate dielectric is directly exposed to plasma and intensively irradiated by energetic particles such as ions, electrons, and photon. Such an irradiation creates plasma damage, which degrades the reliability of gate dielectric. Previously, several attempts were made to prevent plasma damage caused by sputtering deposition process. Ushiki et al. 6,7 investigated the effects of ion species in sputtering deposition on the gate oxide reliability, and showed that Xe plasma sputtering deposition suppresses plasma-induced gate oxide damage by reducing the physical bombardment energy of Xe ion as compared to Ar plasma deposition. Takeuchi et al. demonstrated that the introduction of plasma charge trap to dc-magnetron sputtering system effectively suppresses high-energy particle bombardment to gate dielectric, leading to the improvement in the gate oxide integrity of Mo-gated p-type metal-oxide-semiconductor field-effect transistors ͑PMOSFETs͒ and retention characteristics of Mo-gated nonvolatile memory device. 8 It was also reported that the atomic-layer-deposited buffer layer on which metal gate was sputter deposited was effective in minimizing plasma damage to underlying ultrathin dielectric film. 9 In this work, a comparative study on electrical and structural properties between W/Er/SiO 2 and Pt/SiO 2 gate stacks was performed. It is shown that the interfacial reaction between Er and SiO 2 films of W/Er/SiO 2 gate stacks could be responsible for the reduc...