eRSA: An energy-efficient Reconfigurable Sorting Accelerator

Wu, Junning; Li, Renwei; Feng, Shanggong

doi:10.1109/eitce47263.2019.9094818

Cited by 3 publications

(1 citation statement)

References 8 publications

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“…Accelerators are extensively used for many intensive computational tasks, reducing execution time and energy consumption. Different companies and research groups are developing accelerators in RISC-V for various applications such as digital signal processing [7], artificial intelligence [8,9], and solving mathematical algorithms [10,11]. Among heavy computational tasks, the calculation of trigonometric functions is widely used, especially in digital signal processing algorithms of wireless and communication systems such as WiMAX [12], 3GPP-LTE [13], MIMO [14], CDMA [15], OFDM [16] and WLAN [17].…”

Section: Introductionmentioning

confidence: 99%

A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction

Nguyen

Kiet

Hoang

et al. 2021

IEICE Electron. Express

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This work presents a 32-bit Reduced Instruction Set Computer fifth-generation (RISC-V) microprocessor with a COordinate Rotation DIgital Computer (CORDIC) accelerator. The accelerator is implemented inside the core and being used by the software via custom instruction. The used microprocessor is the VexRiscv with the Instruction Set Architecture (ISA) of RV32IM; that means 32-bit RISC-V including Integer and Multiplication. The experimental results were collected using Field-Programmable Gate Array (FPGA) on the DE2-115 development kit and Application Specific Integrated Chip (ASIC) synthesizer on 180-nm CMOS process library.

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