ESD latency effects in CMOS integrated circuits

Abstract

A series of measurements were performed on two types of commercially available and custom made CMOS integrated circuits to investigate the latent mode of failure due to ESD. The current injection test method was used for both polarities of discharge. Tests parameters studied included: threshold failure, constant aniplitude multiple stress, step stress, and the stress hardening effect.Statistical analyses of the results demonstrate the presence of latent failure in CMOS integrated circuits due to ESD. The work is used to further expand a charge injection model for latent failures.