ESD Power Clamps

Abstract

An electrostatic discharge (ESD) design practice is the integration of ESD power clamps between the power supply rails. ESD power clamps popularity occurred in the 1990s to achieve better ESD results in semiconductor chips [1][2][3][4][5][6]. By mid 1990s, diode string [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17], 3,[20][21][22][23][24][25][26][27], and bipolar ESD power clamps [43][44][45][46][47][48][49], and silicon-controlled rectifiers [50-60] became part of the ESD design methodology and practice. From 1995 to 2005, the focus on the MOSFET ESD power clamps have been on producing a better ESD power clamp, design integration, physical placement [33][34][35][36], and low leakage [38]. In the other technologies, the focus has been extending the concepts to triple-well CMOS [11,12], BiCMOS, silicon germanium [10,[13][14][15][45][46][47], gallium arsenide [48,49], and silicon-oninsulator (SOI) technologies [17][18][19]. ESD power clamps achieve both functional and ESD advantages. ESD power clamps achieve ESD robustness and electrical overstress (EOS) robustness by enhancing the ESD design practice as follows:Establishment of ESD Current Loops: The addition of power clamps provides an alternative current loop for the ESD current.Bidirectional Current Paths: Bidirectional current flow allows the flow of the ESD current through the loop in both directions.Segmented Chip Current Path: ESD power clamps can be placed between independent and disconnected chip segments allowing electrical connectivity.Rail-to-Rail ESD Protection: Rail-to-rail ESD protection between the two power rails is achieved using the power clamp placed between the two power rails.Pin-to-Pin ESD Protection: Pin-to-Pin ESD protection is achieved by establishing bidirectional current paths from the first pin, through the power clamp and to the second pin. ESD: Circuits and Devices Steven H. Voldman