Estimation and optimization of reliability of noisy digital circuits

Abstract

Abstract-With continued scaling, reliability is emerging as a critical challenge for the designers of digital circuits. The challenge stems in part from the lack of computationally efficient techniques for analyzing and optimizing circuits for reliability. To address this problem, we propose an exact analysis method based on circuit transformations. Also, we propose a hybrid method that combines exact analysis with probabilistic measures to estimate reliability. We use such measures in a rewiring-based optimization framework to optimize reliability. Our hybrid approach offers a speedup of 56X when compared to a pure Monte Carlo simulation-based approach with only a 3.5% loss in accuracy. Our optimization framework improves reliability by about 10% accompanied by a 6.9% reduction in circuit area 1 .

Gate-Level Circuit Reliability Analysis: A Survey

“…Therefore, it may not be worthwhile to calculate more correlation coefficients for slightly improved accuracy. In [30], the relative error for large circuits (with hundreds of gates) was reported at ∼7% on average with the runtime of ∼10 s, which is comparable to those from [26].…”

“…CCM is a widely used approach that evaluates the signal probabilities for (fault-free) combination circuits [30]. As mentioned before, the reliability analysis can be transformed to signal probability computation.…”

“…As mentioned before, the reliability analysis can be transformed to signal probability computation. Therefore, the CCM can be used to evaluate the reliability estimation [8,[26][27][28]30]. The main idea of CCM is briefly described below.…”

Reliability evaluation of logic circuits based on transient faults propagation metrics

“…Therefore, reliability evaluation approaches and soft error rate (SER) analysis of logic circuits are needed to meet the increasing demand on reliable design [4,5]. The general definition of reliability is the probability of the correct functioning of a circuit, while SER has been used as a measure on the circuit's vulnerability under the influence of soft errors.…”

Reliability evaluation of logic circuits using probabilistic gate models

“…Recent researches have focused on the use of Markov random fields [11], probabilistic model checking (PMC) [12], probabilistic transfer matrices (PTMs) [13], Bayesian networks [14], analytical and scalable approaches [15], probabilistic decision diagrams (PDDs) [16], Boolean difference calculus [17], signal probabilities [18], circuit transformations [19] and multiple passes for sequential circuits [20]. Several of these approaches, such as those using PMC [12], PTMs [13] and PDDs [16], provide accurate evaluation results, however, they are affected by the problems of state space explosion and an exponential complexity, which make them practically infeasible to be used for large circuits.…”