Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout Mechanisms

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Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout Mechanisms

Cited by 3 publications

References 24 publications

A library based on deep neural networks for modeling the degradation of FinFET SRAM performance metrics due to aging

A library based on deep neural networks for modeling the degradation of FinFET SRAM performance metrics due to aging

CacheEM: For Reliability Analysis on Cache Memory Aging Due to Electromigration

Optimal Accelerated Test Framework for Time-Dependent Dielectric Breakdown Lifetime Parameter Estimation

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