Evaluating Statistical Power Optimization

Abstract

Abstract-In response to the increasing variations in integrated-circuit manufacturing, the current trend is to create designs that take these variations into account statistically. In this paper, we quantify the difference between the statistical and deterministic optima of leakage power while making no assumptions about the delay model. We develop a framework for deriving a theoretical upper bound on the suboptimality that is incurred by using the deterministic optimum as an approximation for the statistical optimum. We show that for the mean power measure, the deterministic optima is an excellent approximation, and for the mean plus standard deviation measures, the optimality gap increases as the amount of inter-die variation grows, for a suite of benchmark circuits in a 45 nm technology. For large variations, we show that there are excellent linear approximations that can be used to approximate the effects of variation. Therefore, the need to develop special statistical power optimization algorithms is questionable.

Stochastic logical effort as a variation aware delay model to estimate timing yield

“…We have considered both inter-and intra-die variations as both share a similar portion of the statistical process variations [5,12]. Half of the variation is assumed to come from inter-die and the other half from intra-die variations.…”