Evaluating the Impact of On-Chip Centre-Tapped Symmetrical Inductor in the Design of Cross-coupled Oscillators.

Abstract

Oscillators are an integral part of many analog, digital, mixed-signal circuits used in signal/clock generators, PLL, and power clock generators. Cross-coupled LC oscillators are preferred more due to their low-phase noise characteristics. The objective of the proposed paper is to analyse the impact of on-chip Inductor characteristics on the design of the cross-coupled NMOS, PMOS, and CMOS oscillators for oscillation frequency 2.23GHz using an on-chip symmetrical inductor available in gpdk45nm technology with inductance 5nH and capacitance 1.02024pF. For analysis, two variations of inductors are used namely, Ind_A with \({R}_{i}=40.5\mu\) and N=5 and Ind_B with \({R}_{i}=22.5\mu\) and N=7. The proposed circuit preferred PMOS-CAP over NMOS-CAP to obtain large capacitance for the same width and supply voltage. The design and simulations are carried out in the cadence tool in 45nm technology. The inductor characteristics such as self-resonating frequency (SRF), quality factor(Q), bandwidth (BW) parasitic resistance (\({R}_{P})\) and capacitance (\({C}_{P})\) are extracted from the simulation. The simulation result shows that the inductor Ind_B has a higher quality factor, higher parasitic capacitance, lower SFR, and lower parasitic resistance than Ind_A. the oscillators incorporated Ind_B have higher output voltage swing, lower phase noise and higher Total Harmonic Distortion (THD) % than the oscillators incorporated Ind_A. In layout design, the whole circuit is designed within dimensions 200µx150µ, the dimension of Ind_A is 152.4µx146µ and Ind_B is 134.4µx128µ respectively. Parasitic resistance is reduced by using multiple metal layers alternatively. Hence, the post-layout results have variation less than 4% compared to pre-layout results.