Evaluating the Impact of Process Variability and Radiation Effects on Different Transistor Arrangements

Brendler, Leonardo H.; Zimpeck, Alexandra L.; Meinhardt, Cristina; Reis, Ricardo

doi:10.1109/vlsi-soc.2018.8644828

Cited by 6 publications

(1 citation statement)

References 21 publications

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“…Previous experiments also considered topologies using only NOR2 and a mix of NAND2-NOR2-INV. However, the only NAND2 topology proved to be better, and it was chosen for this study [38]. Table 1 and Table 2 present the logic functions and the equations for the complex gate version and the converted multi-level logic composed by NAND2 version, respectively.…”

Section: Methodsmentioning

confidence: 99%

Process Variability Impact on the SET Response of FinFET Multi-level Design

Brendler¹,

Zimpeck²,

Meinhardt³

et al. 2020

IFIP Advances in Information and Communication Technology

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Challenges were introduced in integrated circuits design due to the technology scaling. The evolution of integrated circuits has made them more susceptible to the radiation effects, besides increasing the manufacturing process variability. These challenges can lead to circuits operating outside their specification ranges. Transistor arrangement influences the performance of logic cells; complex logic gates can be used to minimize area, delay and power consumption. However, with the increasing relevance of nanometer challenges, it is necessary also to consider these factors at logic level design. This work explores different transistor arrangements for a set of logic functions at the layout level to evaluate the SET response under the process variability. The process variability is analyzed through the work-function fluctuations of the metal gate. The complex gate and the multi-level of NAND2 topologies, that implement the same function, were designed using the 7nm FinFET ASAP7 Process Design Kit. Results show that the multi-level topology is more robust to the radiation effects at both ideal fabrication process and considering the process variability impact. The LETth value considering the multi-level topology is on average 55% higher than the values considering the complex topology. Moreover, all the logic functions analyzed independently of the topology are more sensitive to the SETs considering the impact of the process variability.

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Section: Methodsmentioning

confidence: 99%

Process Variability Impact on the SET Response of FinFET Multi-level Design

Brendler¹,

Zimpeck²,

Meinhardt³

et al. 2020

IFIP Advances in Information and Communication Technology

Self Cite

View full text Add to dashboard Cite

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Challenges in the Design of Integrated Systems for IoT

Reis

2020

IFIP Advances in Information and Communication Technology

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The Internet of Things is moving fast to be the Internet of Everything. This brings several challenges in several areas of Computing Systems, as in Embedded Systems, Computer Architectures, Fault Tolerance and Integrated Circuits and Systems. One common point is the power optimisation, as the demanding energy is increasing year by year. Optimisation must be done in all levels of design abstraction, system, computer architecture till the physical design. Another issue is reliability and fault tolerance as systems at ground level can be affected by radiations reaching the ground. Also, as several devices in IoT are related to sensitive applications, security is also an important issue in different design levels, including the physical one. The talk will present an overview of all these issues, proposing also some solutions.

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