Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs

Chang, Kuei-Chung; Shen, Jih-Sheng; Chen, Tien-Fu

doi:10.1145/1146909.1146950

Cited by 36 publications

(15 citation statements)

References 20 publications

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“…The router consists of packet process units (ingress and egress), an arbitration unit, and a switch fabric, and it provides a robust data transfer medium for the functional IP modules. Another solution for scalable architectures is to use circuit-switched NoC [6][7][8]. Chang [8] proposed a circuit-switched interconnection architecture which uses crossroad switches to construct dedicated channels dynamically between any pairs of cores for application-specific SoCs with few tens of cores.…”

Section: Related Workmentioning

confidence: 99%

Reliable network-on-chip design for multi-core system-on-chip

Chang

2009

J Supercomput

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Network-on-chip (NoC) architectures must deliver good latency-through put performance in the face of tight power and area budgets. However, in highperformance chip design, a significant design challenge is how to fulfill the requirements of circuit noise elimination, since the faults will slow down performance and dissipate much of the overall system power. This paper presents a simple coding scheme for reducing power dissipation, crosstalk noise, and crosstalk delay on the bus while simultaneously detecting errors at runtime. It uses a simple bus-invert encoding technique to reduce the prohibited transitions in terms of crosstalk noise and power dissipation. We also design a corresponding detector to detect errors at the input of the NoC routers. It can save energy by interrupting communications without storing and routing the packets when errors occur during transmissions. The experimental results for various multimedia applications show significant reduction in the number of patterns that are most likely to produce crosstalk errors. The results also show that it is attractive in terms of cost to apply the detecting logic to routers in the NoC with respect to the power consumption.

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Section: Related Workmentioning

confidence: 99%

Reliable network-on-chip design for multi-core system-on-chip

Chang

2009

J Supercomput

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“…The application task graphs of the 12-node MPEG4, the eight-node PIP, the 12-node VOPD, the 12-node MWD were taken from [22]. The task graph of the six-node MPEG4 specification was taken from [23]. The task graphs of the MJPEG and Wavelet applications were taken from [21].…”

Section: Mjpeg Examplementioning

confidence: 99%

“…• Communication patterns of different applications represent different logical topologies. Figure 2 depicts task graphs of realistic applications taken from [21][22][23][24], where numbers on links represent the traffic loads (or required bandwidth). The numbers between braces in the depicted topologies indicate the number of nodes and the number of required links.…”

Section: Introductionmentioning

confidence: 99%

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Design Trade-offs in Customized On-chip Crossbar Schedulers

Hur

Wong

Stefanov

2008

J Sign Process Syst Sign Image Video Technol

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In this paper, we present a design and an analysis of customized crossbar schedulers for reconfigurable on-chip crossbar networks. In order to alleviate the scalability problem in a conventional crossbar network, we propose adaptive schedulers on customized crossbar ports. Specifically, we present a scheduler with a weighted round robin arbitration scheme that takes into account the bandwidth requirements of specific applications. In addition, we propose the sharing of schedulers among multiple ports in order to reduce the implementation cost. The proposed schedulers arbitrate on-demand (at design time) interconnects and adhere to the link bandwidth requirements, where physical topologies are identical to logical topologies for given applications. Considering conventional crossbar schedulers as reference designs, a comparative performance analysis is conducted. The hardware scheduler modules are parameterized. Experiments with practical applications show that our custom schedulers occupy up to 83% less area, and maintain better performance compared to the reference schedulers.

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“…For example, while compression of contents in [54] saved power consumption for off-die bus communication, compression may need more power for on-die and short-distance communication. Yet another example is shown in [18]. Because of communication localities and the latencies, circuit-switched NoC is sometimes more attractive than the traditional packet-switched NoC.…”

Section: Network-on-chipmentioning

confidence: 99%

Trend and Challenge on System-on-a-Chip Designs

Chen

Kung

2007

J Sign Process Syst Sign Image Video Technol

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The success of system-on-a-chip (SoC) hinges upon a well-concerted integrated approach from multiple disciplines, such as device, design, and application. From the device perspective, rapidly improving VLSI technology allows the integration of billions of transistors on a single chip, thus permitting a wide range of functions to be combined on one chip. From the application perspective, numerous killer applications have been identified, which can make full use of the aforementioned functionalities provided by a single chip. From the design perspective, however, with greater device integration, system designs become more complex and are increasingly challenging to design. Moving forward, novel approaches will be needed to meet these challenges. This paper explores several new design strategies, which represent the current design trends to deal with the emerging issues. For example, recognizing the stringent requirements on power consumption, memory bandwidth/ latency, and transistor variability, novel power/thermal management, multi-processor SoC, reconfigurable logic, and design for verification and testing have now been incorporated into modern system design. In addition, we look into some plausible solutions. For example, further innovations on scalable, reusable, and reliable system architectures, IP deployment and integration, on-chip interconnects, and memory hierarchies are all anticipated in the near future.

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Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs

Cited by 36 publications

References 20 publications

Reliable network-on-chip design for multi-core system-on-chip

Reliable network-on-chip design for multi-core system-on-chip

Design Trade-offs in Customized On-chip Crossbar Schedulers

Trend and Challenge on System-on-a-Chip Designs

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