Evaluation of a Heterogeneous Multicore Architecture by Design and Test of an OFDM Receiver

NouriSajjad,; Hussain, Waqar; Nurmi, Jari

doi:10.1109/tpds.2017.2706691

Cited by 16 publications

(7 citation statements)

References 25 publications

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“…CGRAs will also perform their tasks with the same procedure and at the end of the first iteration, the data related to the counted number of clock cycles of four worker-nodes will be retrieved in order to recognize the stored most time consuming CGRA (worst-case). The total number of clock cycles related to the nodes N0, N1, N2 and N8 are equal to 9985, 18039, 1931 and 1685 CC, respectively [30]. Based on the achieved results, node N5 CGRA, which contains the Frequency Offset Estimation block, is the most time consuming one and can be selected as a worst-case candidate by master node N4 RISC core.…”

Section: Performance Equalization By Dfs/dvfs Methodsmentioning

confidence: 99%

“…More information about the execution flow of performing an particular application by the use of template-based CGRAs as well as the application mapping on the HARP platform and the internal structure of the NoC can be found in [30].…”

Section: The Heterogeneous Multicore Platformmentioning

confidence: 99%

“…After passing through N1 and N2 which are associated with Frequency Offset Estimation and FFT, respectively, ending up with N8 CGRA node (at Channel Estimation block). The detail of design and implementation of each block of an OFDM receiver which led to scale CGRAs to different dimensions can be found in [30].…”

Section: Design and Implementation Of An Ofdm Receiver Blocks On Harpmentioning

confidence: 99%

See 2 more Smart Citations

Power mitigation of a heterogeneous multicore architecture on FPGA/ASIC by DFS/DVFS techniques

Nouri

Rossi

Nurmi

2018

Microprocessors and Microsystems

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Section: Performance Equalization By Dfs/dvfs Methodsmentioning

confidence: 99%

Section: The Heterogeneous Multicore Platformmentioning

confidence: 99%

Section: Design and Implementation Of An Ofdm Receiver Blocks On Harpmentioning

confidence: 99%

See 1 more Smart Citation

Power mitigation of a heterogeneous multicore architecture on FPGA/ASIC by DFS/DVFS techniques

Nouri

Rossi

Nurmi

2018

Microprocessors and Microsystems

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“…The LTE OFDM system parameters such as the size of IFFT, the size of the cyclic prefix, and the amount of data to be transferred vary with the change of the channel bandwidth [5]. These different parameters affect the processing time and operations counts [6]. The crucial IFFT and FFT modules are the most computationally intensive blocks compared to other blocks in LTE system [7].…”

Section: Introductionmentioning

confidence: 99%

MIMO-OFDM LTE system based on a parallel IFFT/FFT on NoC-based FPGA

Jallouli

Mazouzi

Diguet³

et al. 2022

Ann. Telecommun.

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The growing demand for wireless devices capable of performing complex communication processes has imposed an urgent need for high-speed communication systems and advanced network processors. This paper proposes a hardware workflow developed for the Long Term Evolution (LTE) communication system. It studies the Multiple-input, multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) LTE system. Specifically, this work focuses on the implementation of the OFDM block that dominates the execution time in high-speed communication systems. To achieve this goal, we have proposed an NoC-based low-latency OFDM LTE multicore system that leverages Inverse Fast Fourier Transform (IFFT) parallel computation on a variable number of processing cores. The proposed multicore system is implemented on an FPGA platform using the ProNoC tool, an automated rapid prototyping platform. Our obtained results show that LTE OFDM execution time is drastically reduced by increasing the number of processing cores. Nevertheless, the NoC's parameters, such as routing algorithm and topology, have a negligible influence on the overall execution time. The implementation results show up to 24% and 76% execution time reduction for a system having 2 and 16 processing cores compared to conventional LTE OFDM implemented in a single-core, respectively. We have found that a 4×4 Mesh NoC with XY deterministic routing connected to 16 processing tiles computing IFFT task is the most efficient configuration for computing LTE OFDM. This configuration is 4.12 times faster than a conventional system running on a single-core processor.

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“…e major drawback of this technique is the synchronization problem between multiple transmitters that may result in low-reliability [19]. Among the aforementioned schemes, OFDMA promises some advantages that the researchers have encouraged to use this modulation as the multiple access technique for NoCs [15][16][17][18][19][20][21][22]. So, we use an OFDMA-based wireless communication for intrachip wireless links as well as interchip ones.…”

Section: Introductionmentioning

confidence: 99%

Scalable THz Network-On-Chip Architecture for Multichip Systems

Tahanian

Tajary

Rezvani

et al. 2020

Journal of Computer Networks and Communications

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While THz wireless network-on-chip (WiNoC) introduces considerably high bandwidth, due to the high path loss, it cannot be used for communication between far apart nodes, especially in a multichip architecture. In this paper, we introduce a cellular and scalable architecture to reuse the frequencies of the chips. Moreover, we use a novel structure called parallel-plate waveguide (PPW) that is suitable for interchip communication. The low-loss property of this waveguide lets us increase the number of chips. Each chip has a wireless node as a gateway for communicating with other chips. To shorten the length of intra- and interchip THz links, the optimum configuration is determined by leveraging the multiobjective simulating annealing (SA) algorithm. Finally, we compare the performance of the proposed THz multichip NoC with a conventional millimeter-wave one. Our simulation results indicate that when the system scales up from four to sixteen chips, the throughput of our design is decreased about 5.8 % , while for millimeter-wave NoC, this reduction is about 21 % . Furthermore, the average latency growth of our system is only 1 % compared with about 40 % increase for the millimeter-wave NoC.

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Evaluation of a Heterogeneous Multicore Architecture by Design and Test of an OFDM Receiver

Cited by 16 publications

References 25 publications

Power mitigation of a heterogeneous multicore architecture on FPGA/ASIC by DFS/DVFS techniques

Power mitigation of a heterogeneous multicore architecture on FPGA/ASIC by DFS/DVFS techniques

MIMO-OFDM LTE system based on a parallel IFFT/FFT on NoC-based FPGA

Scalable THz Network-On-Chip Architecture for Multichip Systems

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