Evaluation of efficient elastic buffers for network on chip router

Nazir, Liyaqat; Mir, Roohie Naaz

doi:10.1109/icpcsi.2017.8392105

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2022

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“…However, this necessitates the support of large regions as well as hardware. The authors [14] present a NOC-based router in which the virtual channelling buffer method plays a critical role in network mesh performance. Romanov, A. Yu.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation 4x4 Network on Chip (NoC) using FPGA

Al-Azzwai¹,

Al-Hilali²,

Jumma³

2022

PEN

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Network on Chip is one of the most crucial in the development of the networks and routers in new days due to the improvement that make through way of sending huge packets of data and technology and protocol that used for sending the packets between IP cores. Also, the NoC is removed the old ways of technique and protocols of sending packets through routers. The NoC is the most enhanced and efficient in working in parallel ways. Hence, Field Program Gate Array (FPGA) is used in the designing of router that its architecture depending on the NoC. The research proposed in this paper proposed 4x4 nodes router with mesh network that support two-dimensional architecture. A real time test is used for experimental through FPGA and the test verified efficient packets transporting via two array buffers that integrated in the proposed router architecture.

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Section: Introductionmentioning

confidence: 99%