Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture

Abstract

This paper presents an evaluation of multiple-valued packet multiplexing scheme for a Network-on-Chip (NoC) architecture. In the NoC architecture, data is transferred from one Processing Element (PE) to another PE through the routers in the form of a packet. A router, suitable for both the binary and the multiple-valued packets, is constructed using the Multiple Valued Source-Coupled Logic circuits. A packet is composed of flag, destination PE address and data fields. In the NoC architecture, packets are generated by microprogram control. In the proposed scheme, two binary packets are multiplexed if the destination PE addresses are the same. Based on address matching, packets are transferred from a source PE to a destination PE autonomously. As a result, the total number of packets can be reduced. The router is designed using 0.18μm CMOS design rule. HSPICE simulation results show that the delay of the router is significantly small for high speed packet transfer. Reduction of microprogram control storage is remarkable in the proposed scheme, because the data transfer can be done autonomously. The advantage is evaluated by simple analysis, and comparison with a conventional pipelined bus architecture is done.