Evidence for recombination at oxide defects and new SILC model

Ielmini, Daniele; Spinellii, A.S.; Lacaita, A.L.; Ghidini, G.

doi:10.1109/relphy.2000.843891

“…of gate electrons tunneling into bulk-oxide traps (mechanism 1 in figure 11) and the recombination of these electrons with substrate holes (mechanism 2 in figure 11). The number of substrate holes, which is temperature dependent, controls the INE mechanism, and we have shown that the gate current is temperature dependent in the voltage range 0 to −1 V. This interpretation is in agreement with the model originally proposed by Ielmini et al [3,4,28,29].…”

Section: Neutral Tat and Lvsilcsupporting

confidence: 92%

Low voltage stress-induced leakage current and traps in ultrathin oxide (1.2–2.5 nm) after constant voltage stresses

Petit¹,

Zander²

2007

Semicond. Sci. Technol.

1

0

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It has been shown that the low voltage gate current in ultrathin oxide metal-oxide-semiconductor devices is very sensitive to electrical stresses. Therefore, it can be used as a reliability monitor when the oxide thickness becomes too small for traditional electrical measurements to be used. In this work, we present a study on n-MOSCAP devices at negative gate bias in the direct tunneling (DT) regime. If the low voltage stress-induced leakage current (LVSILC) depends strongly on the low sense voltages, it also depends strongly on the stress voltage magnitude. We show that two LVSILC peaks appear as a function of the sense voltage in the LVSILC region and that their magnitude, one compared to the other, depends strongly on the stress voltage magnitude. One is larger than the other at low stress voltage and smaller at high stress voltage. From our experimental results, different conduction mechanisms are analyzed. To explain LVSILC variations, we propose a model of the conduction through the ultrathin gate oxide based on two distinctly different trap-assisted tunneling mechanisms: inelastic of gate electron (INE) and trap-assisted electron (ETAT).

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“…Secondly, the TAT inelastic current is given by the equilibrium of gate electrons tunneling into bulk-oxide traps (mechanism 1 in figure 11) and the recombination of these electrons with substrate holes (mechanism 2 in figure 11). The number of substrate holes, which is temperature dependent, controls the INE mechanism, and we have shown that the gate current is temperature dependent in the voltage range 0 to −1 V. This interpretation is in agreement with the model originally proposed by Ielmini et al [3,4,28,29].…”

Section: Neutral Tat and Lvsilcsupporting

confidence: 92%

Periodic Phenomena in Photosynthesis

Chernavskaya¹,

Chernavskii²

1961

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It has been shown that the low voltage gate current in ultrathin oxide metal-oxide-semiconductor devices is very sensitive to electrical stresses. Therefore, it can be used as a reliability monitor when the oxide thickness becomes too small for traditional electrical measurements to be used. In this work, we present a study on n-MOSCAP devices at negative gate bias in the direct tunneling (DT) regime. If the low voltage stress-induced leakage current (LVSILC) depends strongly on the low sense voltages, it also depends strongly on the stress voltage magnitude. We show that two LVSILC peaks appear as a function of the sense voltage in the LVSILC region and that their magnitude, one compared to the other, depends strongly on the stress voltage magnitude. One is larger than the other at low stress voltage and smaller at high stress voltage. From our experimental results, different conduction mechanisms are analyzed. To explain LVSILC variations, we propose a model of the conduction through the ultrathin gate oxide based on two distinctly different trap-assisted tunneling mechanisms: inelastic of gate electron (INE) and trap-assisted electron (ETAT). P g = J /J 0 Q inj , where J is the SILC and is equal to (J − J 0 ) (J 0 and J are the gate current before and after stress, respectively) and Q inj is the injected charge. However, some authors [3] have addressed the LVSILC in terms of J alone, by both characterization, analysis of stress dependence and numerical simulation. They think that the relevance of the LVSILC is simply a consequence of the suppression of direct tunneling current (i.e., virgin) in the voltage range. They propose an alternative interpretation based on the recombination and trap-assisted tunneling (RTAT) model [4]. In this work, we study the relative increase of the gate current, normalized SILC or J /J 0 , to compare and analyze our results with those obtained by various authors using this method.The gate oxide lifetime is undeniably a crucial issue for thinner oxides (t ox 2 nm) [5]. Oxide reliability is characterized by the charge or the time to breakdown at the operating voltage. These quantities are reached by extrapolation from oxide lifetime data obtained under

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“…Reliability issues include several different mechanisms of charge loss and fluctuation, such as Stress-Induced Leakage Current (SILC) through the tunnel oxide [5,6], charge trapping in the dielectrics after cycling, charge de-trapping from the tunnel oxide [7], Random Telegraph Noise (RTN) [8], high temperature charge loss and charge sharing between cell through the inter-poly dielectric [9]. Word Line (WL) -substrate short and fast erase bit impact device reliability short term and are usually screened at wafer sorting.…”

Section: Cell Structure and Operationmentioning

confidence: 99%