Abstract:In this paper we describe a toolfor designing highperformance digital systems. The system is described behaviorally in VHDL and then translated into data flow graph (DFG) structure which captures all control and data flow dependencies of the given behavioral description. Then the design process goes through architecture selection, scheduling, pipelining and component selection processes. As it enters each step, it is explored by a local exploration scheme. The set of developed algorithms tested with standard b… Show more
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