Exact design for the settling time of two-stage Miller compensated operational amplifiers

Abstract

Most of the currently existed settling time design methods for the Miller-compensated two-stage operational amplifiers are based on the approximate analytical model and can obtain only inaccurate results. This paper presents an approach for the exact settling time design for this widely used circuit. By the compensation of the errors in the analytical settling behavior model and executing the conventional design procedure repeatedly, an iterative design scheme is developed. The overall errors are removed by the exact performance computation with the SPICE simulation and the accurate MOS model based sizing in the entire design process. Taking advantage of the fast convergence and precision feature of this method, an efficient process variation-aware design algorithm is further presented. Simulated design results for the amplifiers in 0.18 lm and 90 nm technology are provided to illustrate the effectiveness of the proposed method.