Experience Report: Evaluating Fault Detection Effectiveness and Resource Efficiency of the Architecture Quality Assurance Framework and Tool

Johnsen, Andreas; Lundqvist, Kristina; Hänninen, Kaj; Pettersson, Paul; Torelm, Martin

doi:10.1109/issre.2017.31

Cited by 3 publications

(5 citation statements)

References 16 publications

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Section: Discussionmentioning

confidence: 98%

“…That said, we should consider all the performance aspects when modeling performance requirements. Efficiency was the least studied (found in one paper [39]), and the least quantified in (3) requirements (Figure 8). However, efficiency was specified in (13) requirements, from which we conclude that efficiency is difficult to document and quantify.…”

Section: Discussionmentioning

confidence: 99%

“…We found a total of 180 missing parameters in the analyzed requirements. The majority of them (100) were related to resource constraints, followed by capacity (39), time behavior (22), and throughput/speed (19). No missing parameters for efficiency requirements were detected.…”

Section: Sample Study -Model Evaluationmentioning

confidence: 99%

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An approach for performance requirements verification and test environments generation

2022

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Model-based testing (MBT) is a method that supports the design and execution of test cases by models that specify the intended behaviors of a system under test. While systematic literature reviews on MBT in general exist, the state of the art on modeling and testing performance requirements has seen much less attention. Therefore, we conducted a systematic mapping study on model-based performance testing. Then, we studied natural language software requirements specifications in order to understand which and how performance requirements are typically specified. Since none of the identified MBT techniques supported a major benefit of modeling, namely identifying faults in requirements specifications, we developed the Performance Requirements verificatiOn and Test EnvironmentS generaTion approach (PRO-TEST). Finally, we evaluated PRO-TEST on 149 requirements specifications. We found and analyzed 57 primary studies from the systematic mapping study and extracted 50 performance requirements models. However, those models don’t achieve the goals of MBT, which are validating requirements, ensuring their testability, and generating the minimum required test cases. We analyzed 77 Software Requirements Specification (SRS) documents, extracted 149 performance requirements from those SRS, and illustrate that with PRO-TEST we can model performance requirements, find issues in those requirements and detect missing ones. We detected three not-quantifiable requirements, 43 not-quantified requirements, and 180 underspecified parameters in the 149 modeled performance requirements. Furthermore, we generated 96 test environments from those models. By modeling performance requirements with PRO-TEST, we can identify issues in the requirements related to their ambiguity, measurability, and completeness. Additionally, it allows to generate parameters for test environments.

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Section: Discussionmentioning

confidence: 98%

Section: Discussionmentioning

confidence: 99%

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An approach for performance requirements verification and test environments generation

2022

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“…a single cell and two cells fault models. For single-cell fault model, it consists of Stuck-At Fault (SAF), Transition Fault (TF), and Data Retention Fault (DRF) [10][11][12].…”

Section: Memory Fault Detection Algorithmsmentioning

confidence: 99%

“…There are various memory test algorithms were introduced to test the memory devices [6,[10][11][12]. The conventional test algorithms are zero-one and checkboard scan tests.…”

Section: Introductionmentioning

confidence: 99%

VHDL Modelling of Low-CostMemory Fault Detection Tester

Chun

Leong

Yoong

et al. 2020

JETAP

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Memory modules are widely used in varies kind of electronics system design. The capacity of the memory modules has increased rapidly since the past few years in order to satisfy the high demand from the end-users. The memory modules’ manufacturers demand more units of automatic test equipment (ATE)to increase the production rate. However, the existing ATE used in the industry to carry out the memory testing is too costly(at least a million dollars per ATE tester). The low-cost memory testers are urgently needed to increase the production rate of the memory module. This has in spired us to design a low-cost memory tester. A low-cost memory fault detection tester with all the major fault detection algorithms that used in industry is modelled using Very High Speed Integrated Circuit Hardware Description Language (VHDL) in this paper to support the need of the low-cost ATE memory tester. The fault detection algorithms modelled are MATS+ (Modified Algorithm Test Sequence), MATS++, March C, March C-, March X ,March Y, zero-one and checkerboard scan tests. PERL program is used to analyse the simulation results and a log file will be generated at the end of the memory test. Extensive simulation and experimental test results show that the memory tester modelled covers all the memory test algorithms used in the industry. The low-cost memory fault detection tester designed provides the 100% fault detection coverage for all memory defects.

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