Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack, including the transient measurements

Matsumoto, Keiji; Ibaraki, Soichiro; Sueoka, Kuniaki; Sakuma, Katsuyuki; Kikuchi, Hidekazu; Orii, Yasumitsu; Yamada, Fumiaki

doi:10.1109/stherm.2012.6188819

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Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack, including the transient measurements

Abstract: For the thermal management of three-dimensional (3D

Cited by 19 publications

References 9 publications

Dream Chip Project at ASET

Dream Chip Project at ASET

Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack

Numerical and experimental characterization of the thermal behavior of a packaged DRAM-on-logic stack

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