Experimental Time Evolution Study of the HfO<sub>2</sub>-Based IMPLY Gate Operation

Maestro-Izquierdo, Marcos; Martín-Martínez, J.; Crespo-Yepes, A.; Escudero, M.; Rodrı́guez, R.; Nafría, M.; Aymerich, X.; Rubio, Antonio

doi:10.1109/ted.2017.2778315

Cited by 5 publications

(5 citation statements)

References 24 publications

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“…Converse NonIMPlication (CNIMP) was proposed in [17] and concerns a logic gate design style that improves the well-known IMPLY logic [15] by solving the important issue of incomplete switching of the memristors; the latter was originally stated in [28] and was also observed experimentally [29]. The CNIMP and the SET programming operations together form a universal logic gate set.…”

Section: B Converse Nonimplication (Cnimp)mentioning

confidence: 99%

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Escudero

Vourkas

Rubio

et al. 2019

IEEE Trans. Nanotechnology

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The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this device technology and has so far led to several emerging applications including logic and in-memory computing. Several memristive logic families have been proposed in the current quest for energy-efficient future computing systems. However, the limited device endurance and variability (both cycleto-cycle and device-to-device) are important parameters to be considered in the assessment of logic operations. In this work we used an accurate physics-based model of a bipolar memristor (supporting parasitics of the device structure and variability of switching voltages and resistance states) and demonstrate that performance of memristor-based in-memory computations can de degraded owing to both variability and state drift impact, if such features are not properly considered in the design flow. Inspired on pseudo-NMOS ratioed logic and based upon a CMOS-like logic scheme, we propose a crossbar-compatible memristive ratioed logic style which is tolerant to device variability and does not affect device endurance as computations do not involve conditional switching of memristors. Using the Cadence Virtuoso suite, we compare this logic scheme with MAGIC and CNIMP approaches, focusing on the universal NOR gate and complex logic functions.

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Section: B Converse Nonimplication (Cnimp)mentioning

confidence: 99%

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Escudero

Vourkas

Rubio

et al. 2019

IEEE Trans. Nanotechnology

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“…Memristive stateful logic is a technology capable of performing a Boolean logic operation inside the memory array. [1][2][3][4][5][6][7][8][9] In the ideal stateful logic, the inputs and outputs are the resistance values of the memristor cells at each cross point in the crossbar array, and data are not sent outside of the memory array during operation. This format is known as complete in-memory computing.…”

Section: Introductionmentioning

confidence: 99%

A Universal Error Correction Method for Memristive Stateful Logic Devices for Practical Near‐Memory Computing

Kim

Song

et al. 2020

Advanced Intelligent Systems

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Memristive stateful logic allows complete in‐memory computing and is considered to be a next‐generation computing technology for low power edge applications. Since the first stateful IMP gate was proposed in 2010, few studies have yet addressed the operating reliability issues that should be resolved before the technology is practically realized. Herein, a feasible near‐memory error correction method for a typical bipolar‐type memristor stateful logic system is proposed. An error correction principles using a HfO2‐based crossbar array device is explained, and two types of error correction methods checking if the number of FALSE data is zero and if the number of TRUE data is odd are proposed. Although the error correction modules require additional circuits and processing time, the resulting computing efficiency is comparable with conventional stateful logic techniques. Its application with a one‐bit full adder is demonstrated and its feasibility for practical stateful logic devices is validated.

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“…The functionality of a MAGIC adder has been shown with organic unipolar switching devices 36 . Next to the demonstration of the IMPLY logic in the proposing publication 17 additional publications presented experimental studies for this approaches 37,38 . All of these adders require a certain number of devices and steps to perform a certain operation, e.g.…”

Section: Introductionmentioning

confidence: 99%

Stateful Three-Input Logic with Memristive Switches

Siemon

Drabinski

Schultis

et al. 2019

Sci Rep

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Memristive switches are able to act as both storage and computing elements, which make them an excellent candidate for beyond-CMOS computing. In this paper, multi-input memristive switch logic is proposed, which enables the function X OR (Y NOR Z) to be performed in a single-step with three memristive switches. This ORNOR logic gate increases the capabilities of memristive switches, improving the overall system efficiency of a memristive switch-based computing architecture. Additionally, a computing system architecture and clocking scheme are proposed to further utilize memristive switching for computation. The system architecture is based on a design where multiple computational function blocks are interconnected and controlled by a master clock that synchronizes system data processing and transfer. The clocking steps to perform a full adder with the ORNOR gate are presented along with simulation results using a physics-based model. The full adder function block is integrated into the system architecture to realize a 64-bit full adder, which is also demonstrated through simulation.

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Experimental Time Evolution Study of the HfO₂-Based IMPLY Gate Operation

Cited by 5 publications

References 24 publications

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

A Universal Error Correction Method for Memristive Stateful Logic Devices for Practical Near‐Memory Computing

Stateful Three-Input Logic with Memristive Switches

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Experimental Time Evolution Study of the HfO2-Based IMPLY Gate Operation

Cited by 5 publications

References 24 publications

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

A Universal Error Correction Method for Memristive Stateful Logic Devices for Practical Near‐Memory Computing

Stateful Three-Input Logic with Memristive Switches

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Product

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Experimental Time Evolution Study of the HfO₂-Based IMPLY Gate Operation