Experimental Validation of On-Site Coding Digital Beamformer With Ultra-Wideband Antenna Arrays

Venkatakrishnan, Satheesh Bojja; Papantonis, Dimitrios K.; Akhiyat, Abe; Alwan, Elias A.; Volakis, John L.

doi:10.1109/tmtt.2017.2690451

Cited by 24 publications

(19 citation statements)

References 24 publications

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“…Using the above synchronization scheme, bit error rate (BER) and SNR was simulated. Based on the results in [9,10,15], it can be concluded that above synchronization scheme results in no performance degradation.…”

Section: Clock Synchronization Implementationmentioning

confidence: 93%

“…Using the above synchronization topology, OSCR performance was measured and it was found that there is no overall degradation in OSCR performance due to synchronization issues, as detailed in [9,10,15]. Using the above synchronization scheme, bit error rate (BER) and SNR was simulated.…”

Section: Clock Synchronization Implementationmentioning

confidence: 99%

“…Despite the capability of the evaluation board (AD9576) to generate low jitter clock signals over wide frequency range, it still is not desirable for synchronization implementation in OSCR. By employing external distribution circuit, the hardware requirement increases, thus defeating the novelty of OSCR [8][9][10][11]. Further, the existing FPGA generates signals which results in the required synchronization without any performance degradation.…”

Section: Clock Synchronization Using External Distribution Circuitmentioning

confidence: 99%

“…This is the case with on-site coding receiver (OSCR) [8,9] that combines several of signals into a single ADC using coding technique, as shown in Figure 1. Since a single ADC is used to handle several antennas/paths, errors due to ADC-FPGA synchronization, interchannel skews, and variations within ADCs can be reduced.…”

Section: Introductionmentioning

confidence: 99%

“…Since a single ADC is used to handle several antennas/paths, errors due to ADC-FPGA synchronization, interchannel skews, and variations within ADCs can be reduced. Specifically, in OSCR architecture [9][10][11], all the components are enclosed within a single block making synchronization easier and less prone to errors. Further, using a single FPGA as a master source for synchronization removes the clock skew errors [12].…”

Section: Introductionmentioning

confidence: 99%

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Challenges in Clock Synchronization for On-Site Coding Digital Beamformer

Venkatakrishnan

Alwan

Volakis

2017

International Journal of Reconfigurable Computing

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Typical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors. To recover and reconstruct the received signal, synchronization is required since the analog-to-digital converters (ADCs), digital-to-analog converters (DACs), field programmable gate arrays (FPGAs), and local oscillators are all clocked at different frequencies. In this article, we present a clock synchronization topology for a multichannel on-site coding receiver (OSCR) using the FPGA as a master clock to drive all RF blocks. This approach reduces synchronization errors by a factor of 8, when compared to conventional digital beamformer.

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Section: Clock Synchronization Implementationmentioning

confidence: 93%

Section: Clock Synchronization Implementationmentioning

confidence: 99%

Section: Clock Synchronization Using External Distribution Circuitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Challenges in Clock Synchronization for On-Site Coding Digital Beamformer

Venkatakrishnan

Alwan

Volakis

2017

International Journal of Reconfigurable Computing

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Interference Mitigation for 5G Millimeter-Wave Communications

2019

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We present a novel ultra-wideband low-cost transmit/receive architecture with reduced power and hardware requirements, which includes interference mitigation capabilities and accommodates multiple users. Specifically, a novel encoding approach is introduced to multiplex signals across large bandwidths and achieve secure communication and interference mitigation through spread signals. In this paper, a detailed description of the proposed high data rate system architecture is presented. Simulations are also provided in the presence of high-power interferers with eight concurrent users. To assess the performance and impact of the encoding/decoding process, a noise analysis was conducted for the transmitter and receiver chains. Specifically, bit error rate curves are generated at different stages of the system. The measurements show interference margin ratios improvement by at least 16 dB.

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